体系结构量化研究方法（第二章-1）

Chapter 2 Memory Hierarchy Design

Introduction

Memory Architecture Optimization Problem

[Objective] Memory Demand

• Good data access performance
  • Low data access latency
  • High data access bandwidth
• Low cost & power

[Constraint] Memory Hardware

• Different storage mediums:
  • trade-off in bandwidth, latency, cost, etc.

[Solution] Memory Architecture Design

• Basic Memory Hierarchy
• Cache Optimizations
  • Basic
  • Advanced

Optimization Demand

1. Memory-processor Latency Gap
   1. Single Processor (demand)
      1. memory requests per second
   2. Single Bank DRAM (supply)
      1. DRAM accesses per second

2. Memory-processor Bandwidth Gap
   1. Processor’s peak bandwidth demand grows with # of cores
   2. DRAM’s bandwidth capability grows much slower
      1. Only 8% of the peak processor demand

Hardware Constraints: Trade-off

• Capacity
• Latency & bandwidth
• Power & cost

Memory Hierarchy Basics

Architecture Solution: Memory Hierarchy

Solution: Organize memory system into a hierarchy

• Inclusion property: Incrementally smaller and faster memories, each containing a subset of the memory below it
• Gives the allusion of a large, fast memory being presented to the processor

Why it works: Locality

• Temporal and spatial locality insures that most recent references can be found in a small set
• Performance and coverage are not required concurrently