Macro Test Examples
Example 1 — Basic 1-Cycle Patterns
Verilog Contents:
RAM mem1 (.Dout ({ Dout[7],Dout[6],Dout[5],Dout[4],Dout[3],
Dout[2], Dout[1], Dout[0]}),
.RdAddr ({ RdAddr[1], RdAddr[0] }),
.RdEn ( RdEn ),
.Din ({ Din[7], Din[6], Din[5], Din[4], Din[3],
Din[2], Din[1], Din[0]}) ,
.WrAddr ({ WrAddr[1], WrAddr[0] }), .WrEn ( WrEn ));
ATPG Library Contents:
model RAM (Dout, RdAddr, RdEn, Din, WrAddr, WrEn) (
input (RdAddr,WrAddr) (array = 1 : 0;)
input (RdEn,WrEn) ()
input (Din) (array = 7 : 0;)
output (Dout) (
array = 7 : 0;
data_size = 8;
address_size = 2;
read_write_conflict = XW;
primitive = _cram(,,
_write {,,} (WrEn,,WrAddr,Din),
_read {,,,} (,RdEn,,RdAddr,Dout)
);
)
)
因为Dout声明为“array 7:0”，所以端口列表中的字符串“Dout”相当于“Dout<7>Dout<6>Dout<5>Dout<4>Dout<2>Dout<1>Dout<0”。如果Dout的声明是Dout“array 0:7”，那么字符串“Dout”将与上述扩展相反。模型定义中始终允许使用向量。目前，宏测试输入模式文件中不允许使用矢量，因此如果您重新定义标头中的引脚顺序对于该文件，必须使用标量。可以使用“Dout<7>”、“Dout（7）”或“Dout[7]”来匹配一位向量。
Dofile Contents:
set_system_mode analysis
macrotest mem1 ram_patts2.pat
write_patterns results/pattern2.f -replace
Test File Input (ram_patts2.pat) Contents:
// model RAM (Dout, RdAddr, RdEn, Din, WrAddr, WrEn) (
// input (RdAddr,WrAddr) (array = 1 : 0;)
// input (RdEn,WrEn) ()
// input (Din) (array = 7 : 0;)
//
// output (Dout) (
// array = 7 : 0;
// data_size = 8;
// address_size = 2;
// .....
// Write V1 (data vector 1) to address 0. Data Outputs
// and Read Address are Don’t Cares.
XXXXXXXX XX 0 10101010 00 P
// Read V1 from address 0. Data Inputs and Write Address
// are Don’t Cares.
HLHLHLHL 00 1 XXXXXXXX XX 0
XXXXXXXX XX 0 0x010101 01 P // Write V2 to address 1.
LXLHLHLH 01 1 xxxxxxxx xx 0 // Read V2 from address 1.
Converted Test File Output (results/pattern2.f) Contents:
... skipping some header information ....
SETUP =
declare input bus "PI" = "/clk", "/Datsel",
"/scanen_early", "/scan_in1", "/scan_en",
.... skipping some declarations ....
declare output bus "PO" = "/scan_out1";
最低0.47元/天 解锁文章
扫一扫
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
