Systemverilog | Test Bench Environment | Half Adder

https://www.youtube.com/watch?v=9ygbJ_rjZHU
Systemverilog | Test Bench Environment | Half Adder

https://www.youtube.com/watch?v=1oFlRtw_g18

module half_adder(s,c,a,b);
input a,b;
output s,c;

xor x1(s,a,b);
and a1(c,a,b);
endmodule


class transaction;

rand bit a;
rand bit b;

bit sum;
bit carry;

function void display(string name);
	$display("----------------");
	$display("---%s---------",name);
	$display("----------------");
	$display("a=%0d, c=%0d",a,b);
	$display("sum=%0d, carry=%0d",sum,carry);
	$display("----------------");
	
endfunction

endclass


`include "intf.sv"
`include "test.sv"

module tbench_top;

	intf i_intf();
	test t1(i_intf);
	
	half_adder h1(
		.a(i_intf.a),
		.b(i_intf.b),
		.s(i_intf.sum),
		.c(i_intf.carry