硬盘中出现eula.1028.txt等垃圾文件的原因及是否可删

本文详细解释了一组由VC2008在安装过程中因bug遗留于硬盘根目录的临时文件,包括eula.*.txt、install.res.*.dll、globdata.ini、install.ini、install.exe、VC_RED.cab、VC_RED.MSI和vcredist.bmp等。这些文件并非系统必需,可以安全删除。

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首先要确定以下几点:

1.这些文件都是在硬盘根目录下,而不是在硬盘的某个文件夹里面.

2.伴随eula.1028等这些文件产生的,还有一些install.res.1028.dll 这样和VC_RED这样的文件,并且eula.1028看起来像记事本.

如果以上两点我都说对了.那么请放心,这些文件可以删除的.

这些文件是vc2008在发行组件包安装时产生的临时文件,但这个软件却因为bug问题而错误的将临时文件放到了C盘更目录(本应该是temp目录并会被自动删除的,并且这个bug是微软已知的bug)

以下是可以删除的文件:

9个文本文件 名字分别为 
eula.1028.txt , 
eula.1031.txt , 
eula.1033.txt , 
eula.1036.txt , 
eula.1040.txt , 
eula.1041.txt , 
eula.1042.txt , 
eula.2052.txt , 
eula.3082.txt 。 
九个.dll档 名字分别为 
install.res.1028.dll , 
install.res.1031.dll , 
install.res.1033.dll , 
install.res.1036.dll , 
install.res.1040.dll , 
install.res.1041.dll , 
install.res.1042.dll , 
install.res.2052.dll , 
install.res.3082.dll . 
两个.ini文件,名字分别为 
globdata.ini , 
install.ini 。 
一个.exe文件 名字为 
install.exe 
一个.cab文件 名字为 
VC_RED.cab 
一个.MSI文件 
VC_RED.MSI 
一个BMP图象 名字为 
vcredist.bmp
Using: C:\intelFPGA\20.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off alu -c alu --vector_source="C:/Users/18145/Downloads/alu181/alu181/alu1/Waveform2.vwf" --testbench_file="C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/Waveform2.vwf.vht" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue May 20 11:58:19 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off alu -c alu --vector_source=C:/Users/18145/Downloads/alu181/alu181/alu1/Waveform2.vwf --testbench_file=C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/Waveform2.vwf.vht Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/" alu -c alu Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue May 20 11:58:21 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/ alu -c alu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file alu.vho in folder "C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4641 megabytes Info: Processing ended: Tue May 20 11:58:22 2025 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/alu.do generated. Completed successfully. **** Running the ModelSim simulation **** C:/intelFPGA/20.1/modelsim_ase/win32aloem/vsim -c -do alu.do ** Error: vsim: CreateProcess error: 2 Error.
最新发布
05-21
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