CMOS_VLSI Chapter4 Delay

一些名词
propagation delay:from input pass 50% to output pass 50%
driver/load
slack: positive slack means meets time constraint,otherwise violate
time constraint: register’s set up time and hold time
critical path: we should focus on the delay of critical path

in this chapter the optimization takes place in number of logic stages,use which kind of gates,the W/L of the transistor

RC delay model

• transistor=a switch and a resistor
• usually a unit of NMOS has R resistance
• a unit of PMOS has 2R resistance
• k times width of NMOS means R/k resistance
• k times width of NMOS/PMOS has kR capacitance
• usually an inverter delay=3RC(2RC+RC)

Elmore delay

a unit inverter drives m same inverter?
C=(3+3m)C,R=R

• fanout: C(load)/C(in)
• fanout=1 unit inverter delay=3RC=t
• delay(generalized)=delay/t

FO4: fanout=4 inverter delay: standard unit for delay

• Elmore delay includes p delay and e delay
• parasitic delay: a gate’s effort to drive its own D/S delay(not relevant to sizing)
• effort delay: fanout,how complicated is the gate?(logical effort),sizing

linear delay model

• delay=p+f
• f=gh
• g: logic effort(input capacitance,grow with number of input)
• h: fanout

typical logic effort

for mux: logical effort of mux is always 2,but the p-delay will grow with size,usually,we use 4-input mux

usually FO4 delay is equal to 1/3-1/2 its channel length(in ps)

• 驱动强度：define as C(input)/logical effort
• use driver strength to represent delay:d=Cout/x+p

path effort(delay of multi-stage network)

• path logical effort:G=g1×g2xg3…
• path electrical effort/path fanout H=Cout/Cin
• branching effect:B=(Con+Coff)/Con
• path effort F=GBH

the delay of a path

minimum delay of a path:

choose the number of stages

• the easy way is make each stage effort =4

tips

• how is the delay of a gate defined in particular technology
• making transistor bigger can make load and drive strength both bigger
• always use less stage,not more