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**MMC_仿真模型** 本文将深入探讨MMC（模块化多电平换流器）的Matlab仿真模型，这种技术在高压直流输电（HVDC）系统中占据着重要的地位。MMC因其独特的结构和性能优势，已成为现代电力系统中交流与直流转换的关键技术。 **一、MMC简介** 模块化多电平换流器是一种新型的多电平变流器，由多个子模块（Submodules，SMs）构成，每个子模块包含两个电容器和一个开关元件。这种设计允许生成连续的电压阶跃，减少了传统两电平或三电平换流器的谐波含量。MMC-HVDC系统则利用MMC实现高压直流传输，提高了能源传输的效率和稳定性。 **二、Matlab仿真模型** 在Matlab/Simulink环境中构建MMC的仿真模型，能够对系统性能进行精确分析和预测。模型通常包括以下几个关键部分： 1. **子模块模型**：每个子模块模型包含电容电压控制、开关状态决策以及开关器件的损耗计算。 2. **拓扑控制**：根据系统运行条件，决定子模块的开闭状态，以保持平均电容电压平衡。 3. **直流侧控制**：调整模块的有功功率和无功功率，以满足系统需求。 4. **交流侧控制**：处理与交流电网的接口，包括电压和频率调节。 **三、文件内容解析** - **电压电流.jpg、模型图.jpg**：这些可能是仿真结果的图表，展示MMC运行时的电压和电流波形，用于分析系统动态响应和稳态性能。 - **QQ截图20131226161329.jpg**：可能是一次特定的仿真设置或结果的快照，提供了进一步的可视化信息。 - **yanxuewang.mat**：可能是一个Matlab数据文件，包含了仿真参数或预计算的结果。 - **MMC_CPS_Three_Phase_01.mdl**：这是主仿真模型文件，包含了MMC的三相电路模型。 - **IEEE.2013.05.Voltage Balancing and Fluctuation-Suppression Methods of Floating Capacitors in a New Modular Multilevel Converter.pdf**：这是一篇IEEE论文，详细讨论了浮置电容器的电压平衡和波动抑制方法，是理解MMC内部控制策略的重要参考资料。 **四、电压平衡与波动抑制** 浮置电容器的电压平衡是MMC稳定运行的关键。论文中提出的策略可能涉及实时监测每个子模块的电容电压，通过调整开关状态或注入补偿电流来维持平衡。此外，对于电压波动的抑制，可能涉及到快速的控制系统，如采用预测控制算法，预测并消除电压波动。 MMC-HVDC系统的Matlab仿真模型为理解和优化这种复杂系统提供了强大的工具。通过对模型的深入研究和调整，工程师可以对系统性能进行预测，改进控制策略，以提高系统的可靠性和效率。

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013 1943

Voltage Balancing and Fluctuation-Suppression

Methods of Floating Capacitors in a

New Modular Multilevel Converter

Kui Wang, Member, IEEE, Yongdong Li, Member, IEEE, Zedong Zheng, Member, IEEE, and Lie Xu, Member, IEEE

Abstract—Modular multilevel converter (MMC) is a newly

emerging multilevel topology for high-voltage applications during

recent years. In this paper, a new MMC is proposed, and the

structure and operating principle are analyzed. Owing to the

cascaded basic cells without multiwinding transformer, the voltage

balancing of ﬂoating capacitors must be considered. However, the

voltage ﬂuctuation also exists, and theoretical analysis indicates

that the amplitude is inversely proportional to the fundamen-

tal frequency. This paper has proposed a voltage-ﬂuctuation-

suppression method which can reduce the amplitude of the voltage

ﬂuctuation in low-frequency region. It can also be used in motor

driving with pump/blowerlike load at low frequency and improve

the start-up performance signiﬁcantly. A low-power three-phase

ﬁve-level prototype is designed and built up to demonstrate the

validity of this method.

Index Terms—Floating capacitor, modular multilevel converter

(MMC), voltage balancing, voltage-ﬂuctuation suppression.

I. INTRODUCTION

ULTILEVEL converters receive increasing attentions in

recent years due to the demands of high power and high

voltage in industrial applications [1]–[3]. Plenty of multilevel

topologies have been investigated, but only several of them are

practical for industrial applications [4]–[7]. Among the existing

multilevel converters, diode-clamped and cascaded H-bridge

(CHB) multilevel converters are the most widely used [8]–[14].

For medium-voltage (2.3, 3.3, and 4.16 kV) applications, three-

level neutral-point-clamped (NPC) topology is a good solution

[10], but some problems exist while extending NPC converter

to higher voltage levels, such as mass clamping diodes and

the voltage imbalance of dc-link capacitors [10]–[12]. For

applications with voltage higher than 6 kV, CHB multilevel

inverters are commonly used [10], [13], [14]. In this topology,

a lot of isolated voltage sources are required. To generate

separated voltage sources, conventional method is to employ

a multiwinding transformer with the same number of isolated

secondary windings, which is huge and expensive.

Manuscript received September 27, 2011; revised December 31, 2011 and

February 29, 2012; accepted May 9, 2012. Date of publication May 30, 2012;

date of current version January 30, 2013.

The authors are with the State Key Laboratory of Power System, Department

of Electrical Engineering, Tsinghua University, Beijing 100084, China (e-mail:

[email protected]; [email protected]; [email protected];

[email protected]).

Color versions of one or more of the ﬁgures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/TIE.2012.2201433

Recently, a new multilevel topology gains more and more

attentions in high-voltage applications: modular multilevel con-

verter (MMC) [15]–[25]. It is ﬁrst proposed by Marquardt and

Lesnicar [15] and is regarded as one of the next-generation

high-voltage multilevel converters without line-frequency

transformers [22]. The MMC is suitable for high-voltage power

conversion due to its modular structure, simple voltage scaling,

and common dc bus [15]–[17]. However, it also has some

drawbacks, such as voltage imbalance of ﬂoating capacitors and

acute voltage ﬂuctuation at low frequency [19]–[25]. Reference

[21] proposed a stable voltage control method to realize both

averaging and balancing controls of ﬂoating capacitors. Refer-

ence [22] proposed a start-up method suitable for motor drive

with a pump/blowerlike load. These methods are all based on

phase-shift carrier pulsewidth modulation (PWM) (PS-PWM)

scheme. In order to suppress the low-frequency voltage ﬂuc-

tuation directly, the concept of injecting high-frequency zero-

sequence voltage and circulating current is proposed in [23],

which can be used to start up induction motors (IMs) with

quadratic-torque loads. However, it only considers the dc and

fundamental components in the branch current and ignores the

second-order component, so the calculated circulating current

is very complex and contains two independent parts. What

is more, it does not discuss how to generate the three-phase

circulating currents.

This paper proposes a new MMC which connects the upper

and the lower bridges through a middle cell. In Section II, the

structure and operating principles of the new MMC will be

discussed ﬁrst. Section III presents the modulation scheme and

voltage balancing method of the new MMC. In Section IV,

the voltage ﬂuctuation is studied by theoretical analysis, and

a voltage-ﬂuctuation-suppression method is proposed. Exper-

imental results with both R−L load and IM load are pre-

sented in Section V, and ﬁnally, conclusions are summarized in

Section VI.

II. S

TRUCTURE AND OPERATING PRINCIPLES

Reference [5] proposed a generalized multilevel inverter,

which is regarded as the most complicated and comprehensive

multilevel topology. Ithas been found that the existing multilevel

inverters such as diode-clamped, ﬂying-capacitor, and CHB mul-

tilevel inverters can all be derived from the generalized inverter

topology [5]–[7]. Moreover, obeying some particular rules,

more topologies can be derived from it. Therefore, it provides a

systematic method to study the new multilevel topologies.

1944 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

Fig. 1. Relationship of the proposed new MMC and the generalized multilevel

inverter.

A single phase of the generalized ﬁve-level inverter is shown

in Fig. 1. By conserving the outside basic cells in shadow and

eliminating others, a new multilevel topology can be obtained.

In this new topology, the most attractive feature is that all the

basic cells are independent and connected in series one by one.

This new topology is similar to traditional MMC and so is

named as new MMC. The main difference between them is that

the proposed new MMC employs a middle cell in each phase,

which can reduce the number of basic cells while producing

the same number of voltage levels. Of course, it also has

some drawbacks due to the employment of middle cell, such

as that the voltage balancing becomes more complex and the

redundancy of middle cell is hard to realize.

While extending the new MMC to higher levels, the structure

of a three-phase inverter is shown in Fig. 2. Each phase consists

of 2n +1series-connected basic cells and two buffer inductors.

It can be divided into three parts: upper bridge, lower bridge,

and middle cell. Both the upper and lower bridges contain n

identical basic cells. The middle cell is employed to connect

the upper bridge and lower bridge; consequently, the number of

voltage levels can be extended to n +2.

The structures of upper bridge cell, lower bridge cell, and

middle cell are shown in Fig. 2(b). Each basic cell has two

switching states: on-state and off-state, indicated by a switching

function S. It is deﬁned as follows:

S =



1 (on - state)

0 (off - state)

. (1)

On-state (S =1)means that the upper insulated-gate bipo-

lar transistor (IGBT) is switched on and the lower IGBT is

switched off. Off-state (S =0) means that the upper IGBT

is switched off and the lower IGBT is switched on. For the

upper bridge cells, the capacitor is inserted into the bridge when

S =0and bypassed when S =1. For the lower bridge cells, the

capacitor is inserted into the bridge when S =1and bypassed

when S =0. Thus, the output voltage of each basic cell can be

expressed as follows:



OPi

=(1− S

CPi

ONi

= S

CNi

,i=1, 2,...,n (2)

where u

OPi

, u

CPi

, and S

are the output voltage, capacitor

voltage, and switching function of the ith basic cell in the upper

bridge, respectively, and u

ONi

, u

CNi

, and S

are the output

voltage, capacitor voltage, and switching function of the ith

basic cell in the lower bridge, respectively.

Fig. 2. Structure of the new MMC and its basic cells.

Taking phase a as an example, the dc-link voltage U

can

be expressed as



i=1

OPi

+ u



i=1

ONi

+ l

− i

) (3)

where u

is the voltage of middle-cell capacitor, l is the

bridge buffer inductor, and i

and i

are the upper and lower

bridge currents, respectively.

For the voltage drop across bridge inductor l that is very

small, the last item of (3) can be neglected. Assuming that the

voltage of each capacitor maintains stable and the reference

voltage is

C,ref

(n +1)

(4)

then (3) can be simpliﬁed as



i=1



i=1

. (5)

WANG et al.: VOLTAGE BALANCING AND FLUCTUATION-SUPPRESSION METHODS OF CAPACITORS IN A NEW MMC 1945

Equation (5) indicates that the basic cells of upper and lower

bridges are complementary. When an upper bridge capacitor

is inserted into the bridge, a lower bridge capacitor should be

bypassed. Thus, the total number of capacitors inserted into a

bridge is always n +1.

Taking the negative pole “N” of the dc link as the zero

potential, for a given voltage level k (k =0, 1, 2,...,n+1),

the output voltage can be written as

= kU

C,ref

= S



i=1

CNi

. (6)

Hence,

k = S



i=1

, (k =0, 1,...,n+1) (7)

where S

is the switching function of middle cell.

Based on (5) and (7), the following conclusions can be

obtained.

1) The sums of switching functions of the upper and the

lower bridges must be the same, which means that they

have the same number of basic cells operated at on-state

and off-state.

2) The output voltage level is determined by the sum of

switching functions of the middle cell and the lower

bridge cells.

III. M

ODULATION SCHEME AND VOLTAGE

BALANCING METHOD

A. Modulation Scheme

Several PWM schemes have been suggested to balance the

ﬂoating-capacitor voltages of MMCs, such as space-vector

PWM (SVPWM), PS-PWM, and phase-disposition carrier

PWM (PD-PWM). SVPWM is widely used in two-level and

three-level converters, but it is not practical for higher voltage-

level converters.

PS-PWM is commonly used in CHB inverters and ﬂying-

capacitor multilevel inverters [9]. When using PS-PWM in

MMCs, in order to balance the voltages of all ﬂoating capac-

itors, the reference voltage of each basic cell must be controlled

by an independent proportional–integral-based controller [21].

It turns to be very complex when the number of basic cells is

very high. For PD-PWM scheme, only one reference voltage is

required for each phase, which is easier to be extended to high-

voltage levels.

When PD-PWM is used, the reference voltage is compared

to a group of triangular carrier waveforms. Thus, each basic cell

has three possible operating modes during one PWM interval:

constant at on-state, constant at off-state, and partly constant at

on-state with a duty cycle, which can be denoted by “S =1”

mode, “S =0” mode, and “PWM” mode, respectively.

According to (5), the numbers of “S =1” mode, “S =0”

mode, and “PWM” mode in the upper bridge are the same with

those in the lower bridge, with the addition of middle cell, each

phase should determine n +1 independent operating modes:

one “PWM” mode, some “S =1” modes, and the rest are “S =

0” modes.

Assuming that the region of reference output voltage U

ref

C,ref

ref

< (k +1)U

C,ref

, (k =0, 1,...,n). (8)

Region k is where the magnitude of U

ref

lies, which indicates

that the output voltage level jumps between k and k +1.

Comparing the reference voltage to n +1cascaded triangular

carrier signals with the amplitude of U

C,ref

, n +1independent

operating modes can be obtained: The carrier signals below the

reference voltage correspond to “S =1” mode, those over the

reference voltage correspond to “S =0” mode, and the one

who crosses the reference voltage corresponds to the “PWM”

mode. Therefore, the numbers of “PWM” mode, “1” mode, and

“0” mode are one, k, and n–k, respectively.

B. Voltage Balancing Method

Although the number of “S =1” and “S =0” modes is

determined, which cells operate at “S =0” mode, “S =1”

mode, and “PWM” mode are not speciﬁed. It provides a consid-

erable selectivity to realize the voltage balancing of all ﬂoating

capacitors. Due to the different structures of basic cells, the

voltage balancing can be divided into the following two steps:

1) voltage balancing of middle-cell capacitor;

2) voltage balancing of the inner capacitors in the upper and

lower bridges.

For a particular basic cell, whether its capacitor is charged,

discharged, or bypassed depends on its switching states and

current polarity.

For the basic cells in the upper bridge, the capacitors are

bypassed at on-state and charged at off-state when i

> 0.

For the basic cells in the lower bridge, the capacitors are

discharged at on-state and bypassed at off-state when i

> 0.

For the middle cell, the capacitor is discharged at on-state

and charged at off-state when i

> 0, where i

is the phase

current and is the sum of i

and i

The essential rule of the voltage balancing method is to

assign the operating modes according to their capacitor voltages

and current polarity. First of all, the voltages of all ﬂoating

capacitors are measured and sorted in ascending order. The

average voltages of the upper and lower bridge capacitors

are deﬁned as u

CP,avg

and u

CN,avg

, respectively. In order to

balance the middle-cell voltage, its operating mode must be

considered ﬁrst.

1) If u

CP,avg

and u

CN,avg

, the middle-cell

capacitor should be discharged. If i

> 0, the middle cell

operates at “S =1” mode or “PWM” mode (no “S =1”

mode when k =0); otherwise, it will operate at “S =0”

mode or “PWM” mode (no “S =0” mode when k = n)

if i

< 0.

2) If u

CP,avg

and u

CN,avg

, the middle-cell

capacitor should be charged. If i

> 0, the middle cell

operates at “S =0” mode or “PWM” mode (no “S =0”

mode when k = n); otherwise, it will operate at “S =1”

mode or “PWM” mode (no “S =1” mode when k =0)

if i

< 0.

3) If u

is between u

CP,avg

and u

CN,avg

, it operates at the

previous switching mode.

1946 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

Fig. 3. Flowchart of determining the operating mode of middle cell.

Fig. 4. Flowchart of the voltage balancing method.

The ﬂowchart which describes the operating-mode determi-

nation of the middle cell is shown in Fig. 3. The algorithm

includes comparisons and judgments only. Hence, it takes up

less resource for application.

After specifying the operating mode of the middle cell, the

operating modes of the upper and lower bridge cells can be

determined with the similar method.

When the middle cell operates at “PWM” mode, then k basic

cells of upper/lower bridge operate at “S =1” mode, and the

rest operate at “S =0” mode.

When the middle cell operates at “S =1” mode, then k−1

basic cells of upper/lower bridge operate at “S =1” mode, one

operates at “PWM” mode, and the rest operate at “S =0” mode.

When the middle cell operates at “S =0” mode, then k

basic cells of upper/lower bridge operate at “S =1” mode, one

operates at “PWM” mode, and the rest operate at “S =0” mode.

In order to realize the voltage balancing of the inner capaci-

tors in the upper and lower bridges, the following rules should

be obeyed when assigning these operating modes.

When i

>0(i

>0),“S =1” modes, “PWM” mode, and

“S =0” modes should be assigned to n upper bridge (lower

bridge) cells, respectively, according to their voltages from high

to low.

When i

<0(i

< 0),“S =1” modes, “PWM” mode, and

“S =0” modes should be assigned to n upper bridge (lower

bridge) cells, respectively, according to their voltages from low

to high.

Fig. 4 shows the ﬂowchart of the voltage balancing

method. [u

CP1

CP2

,...,u

CPn

] and [u

CN1

CN2

,...,u

CNn

]

are the upper and lower bridge capacitor voltages, respec-

tively. The vector [U

,...,U

] is a mapping of the

upper bridge capacitor voltages sorted in descending or-

der if i

> 0 and in ascending order if i

< 0.Also,

C(n+1)

C(n+2)

,...,U

C2n

] is a mapping of the lower

bridge capacitor voltages sorted in descending order if i

> 0

and in ascending order if i

< 0.

IV. V

OLTAGE-FLUCTUATION-SUPPRESSION METHOD

A. Theoretical Analysis of Voltage Fluctuation

Although the capacitor voltages of the upper and lower

bridges can be balanced, the voltage ﬂuctuation also exists.

This section will analyze the voltage ﬂuctuation and present a

ﬂuctuation suppression method.

Assuming that the three-phase voltages and currents are

perfectly sinusoidal and symmetrical, then the output phase

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内容反馈

qq_42935759

2021-04-07

只是一个简单的MMC逆变，并不包含其他的东西
qq_38413641

2017-12-04

该模型仅是基于MMC的逆变器
qq_26401737

2018-11-09

还不错，学习下
zhqlin

2017-07-03

该模型仅是基于MMC的逆变器，并不是MMC-HVDC的模型，大家谨慎下载
东北老蜜蜂

2019-03-29

学习一下吧

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