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ADI ADSP-BF536处理器是由Analog Devices公司出品的一款高性能Blackfin处理器，它集成了网络连接功能，支持高达600MHz的处理速度，具备强大的多媒体处理能力，并提供丰富的外设接口。本文将详细介绍这款处理器的关键特性以及其应用领域的相关知识点。 ### 关键特性 1. **Blackfin处理器核心：** - 高性能的Blackfin处理器核心，具有RISC-like的寄存器和指令模型，易于编程且支持编译器。 - 采用600MHz的处理速度，可以满足高级别的计算需求。 - 包含三个16位多媒体加速器(MACs)以及四个8位视频处理加速器，适用于图像和视频处理。 2. **网络连接：** - 符合IEEE 802.3标准的10/100以太网MAC，提供有线网络连接能力。 - 集成控制器局域网络(CAN)2.0B接口，适合工业控制和汽车电子应用。 3. **外围接口：** - 包含2个全双工同步串行端口SPORTs，支持8路立体声I2S通道。 - 集成串行外设接口(SPI)和2个支持IrDA的UARTs，适合与外部设备通信。 - 提供2线接口(TWI)控制器和高达8个带高电流驱动的GPIOs，用于控制外围设备。 4. **内存管理：** - 内置高达132KB的片上内存，包括指令和数据SRAM/Cache，还有额外的专用数据SRAM和临时存储SRAM。 - 支持外部SDRAM和异步8位、16位内存的外部内存控制器，提供灵活的启动选项，包括外部Flash、SPI和TWI存储器或从SPI、TWI和UART主机设备启动。 5. **多功能集成：** - 包含32个中断输入的事件处理控制器。 - 12个外围DMA通道，其中2个由以太网MAC控制，2个内存到内存DMA通道具有外部请求线。 - 具备8个32位定时器/计数器和PWM功能，以及一个实时时钟(RTC)和看门狗定时器。 - 32位核心定时器用于追踪系统运行时间。 6. **电源管理：** - 内置可编程的片上电压调节器。 - 支持0.5至64倍频率的PLL倍频功能，以调节处理器速度。 7. **封装与接口：** - 提供182球和208球的CSP_BGA封装，方便在不同应用场景下使用。 - 提供JTAG测试和仿真接口，便于开发和调试。 ### 应用领域 ADI ADSP-BF536处理器由于其高性能和丰富的外设接口，被广泛应用于包括但不限于以下领域： 1. **工业自动化：** - 适用于要求实时数据处理和控制的工业应用，如机器人控制、自动化测试设备等。 2. **汽车电子：** - 特别适合于车载信息娱乐系统、安全系统和其他嵌入式控制应用。 3. **通信基础设施：** - 以太网MAC支持使其可以用于网络交换设备、路由器和其他网络相关设备。 4. **消费类电子产品：** - 如家庭娱乐设备，包括高清电视、蓝光播放器等。 5. **医疗设备：** - 用于医疗成像设备、监控设备和患者监护系统等。 ### 总结 ADI ADSP-BF536处理器是一款功能强大的嵌入式处理器，专为需要高性能计算能力和丰富网络连接选项的应用而设计。其内建的Blackfin处理器核心、丰富的外设接口以及灵活的内存管理功能，使它成为工业、汽车、通信和消费类电子产品等多个领域的理想选择。通过深入理解这款处理器的特性，设计师能够更好地发挥其潜能，为终端用户带来更强大、更高效的产品体验。

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Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Blackfin

Embedded Processor

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Up to 600 MHz high performance Blackfin processor

Three 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Wide range of operating voltages. See Operating Conditions

on Page 23

Programmable on-chip voltage regulator

182-ball and 208-ball CSP_BGA packages

MEMORY

Up to 132K bytes of on-chip memory

Instruction SRAM/cache and instruction SRAM

Data SRAM/cache plus additional dedicated data SRAM

Scratchpad SRAM (see Table 1 on Page 3 for available

memory configurations)

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI and TWI

memory or from SPI, TWI, and UART host devices

Memory management unit providing memory protection

PERIPHERALS

IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and

ADSP-BF537 only)

Controller area network (CAN) 2.0B interface

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

2 dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting 8 stereo I

S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

2 memory-to-memory DMAs with external request lines

Event handler with 32 interrupt inputs

Serial peripheral interface (SPI) compatible

2 UARTs with IrDA support

2-wire interface (TWI) controller

Eight 32-bit timer/counters with PWM support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), 8 with high current drivers

On-chip PLL capable of 0.5ⴛ to 64ⴛ frequency multiplication

Debug/JTAG interface

Figure 1. Functional Block Diagram

SPORT0

CAN

VOLTAGE REGULATOR

PORT J

GPIO

PORT H

GPIO

PORT G

GPIO

PORT F

JTAG TEST AND EMULATION

PERIPHERAL ACCESS BUS

WATCHDOG TIMER

RTC

TWI

SPORT1

PPI

SPI

TIMER7-0

ETHERNET MAC

(See Table 1)

BOOT ROM

DMA

EXTERNAL

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

DATA

MEMORY

INSTRUCTION

MEMORY

DMA CORE BUS

EXTERNAL ACCESS BUS

EXTERNAL PORT

FLASH, SDRAM CONTROL

UART0-1

Rev. G | Page 2 of 68 | February 2009

ADSP-BF534/ADSP-BF536/ADSP-BF537

TABLE OF CONTENTS

Features ................................................................. 1

Memory ................................................................ 1

Peripherals ............................................................. 1

Table Of Contents .................................................... 2

Revision History ...................................................... 2

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Blackfin Processor Peripherals ................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Port ....................... 10

UART Ports ...................................................... 10

Controller Area Network (CAN) ............................ 11

TWI Controller Interface ...................................... 11

10/100 Ethernet MAC .......................................... 11

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 12

Dynamic Power Management ................................ 13

Voltage Regulation .............................................. 14

Clock Signals ...................................................... 15

Booting Modes ................................................... 16

Instruction Set Description .................................... 17

Development Tools .............................................. 17

Designing an Emulator-Compatible Processor Board ... 18

Related Documents .............................................. 18

Pin Descriptions .................................................... 19

Specifications ........................................................ 23

Operating Conditions ........................................... 23

Electrical Characteristics ....................................... 25

Absolute Maximum Ratings ................................... 29

ESD Sensitivity ................................................... 29

Package Information ............................................ 29

Timing Specifications ........................................... 30

Output Drive Currents ......................................... 52

Test Conditions .................................................. 54

Thermal Characteristics ........................................ 57

182-Ball CSP_BGA Ball Assignment ........................... 58

208-Ball CSP_BGA Ball Assignment ........................... 61

Outline Dimensions ................................................ 64

Surface-Mount Design .......................................... 65

Automotive Products .............................................. 66

Ordering Guide ..................................................... 66

REVISION HISTORY

2/09—Rev. E to Rev. G

The revision F data sheet was never released publicly. The fol-

lowing revisions include those from both revision E to F and

from revision F to G.

Revised the I

DDSLEEP

, I

DDDEEPSLEEP

, and I

DDINT

specifications. See

Electrical Characteristics .......................................... 25

Removed the Power Dissipation section. See Estimating Power

for the ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297)

and Table 16 and Table 15 ........................................ 27

Added t

NOBOOT

specification to Clock and Reset Timing ... 30

Removed DATA15–0 from footnote 1 in Asynchronous Mem-

ory Write Cycle Timing ........................................... 32

Revised SDRAM t

ENSDAT

specification. See SDRAM Interface

Timing ................................................................ 34

Revised serial ports internal clock timing specifications t

SFSI

and t

SDRI

. See Serial Ports ......................................... 39

Revised SPI master timing specifications and diagram.

See Serial Peripheral Interface Port—Master Timing ....... 42

Revised SPI slave timing specifications and diagram.

See Serial Peripheral Interface Port—Slave Timing ......... 43

Revised timer cycle timing specifications t

TIS

and t

TOD

. See Timer

Cycle Timing ......................................................... 46

Revised Figure 61 and Figure 62 (added NC pin). ............59

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. G | Page 3 of 68 | February 2009

GENERAL DESCRIPTION

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are

members of the Blackfin

family of products, incorporating the

Analog Devices, Inc./Intel Micro Signal Architecture (MSA).

Blackfin processors combine a dual-MAC, state-of-the-art sig-

nal processing engine, the advantages of a clean, orthogonal

RISC-like microprocessor instruction set, and single-instruc-

tion, multiple-data (SIMD) multimedia capabilities into a single

instruction-set architecture.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are

completely code and pin compatible. They differ only with

respect to their performance, on-chip memory, and presence of

the Ethernet MAC module. Specific performance, memory, and

feature configurations are shown in Table 1.

By integrating a rich set of industry-leading system peripherals

and memory, the Blackfin processors are the platform of choice

for next-generation applications that require RISC-like pro-

grammability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which is the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. This capability can result in a substantial reduc-

tion in power consumption, compared with just varying the

frequency of operation. This allows longer battery life for

portable appliances.

SYSTEM INTEGRATION

The Blackfin processor is a highly integrated system-on-a-chip

solution for the next generation of embedded network-con-

nected applications. By combining industry-standard interfaces

with a high performance signal processing core, cost-effective

applications can be developed quickly, without the need for

costly external components. The system peripherals include an

IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and

ADSP-BF537 only), a CAN 2.0B controller, a TWI controller,

two UART ports, an SPI port, two serial ports (SPORTs), nine

general-purpose 32-bit timers (eight with PWM capability), a

real-time clock, a watchdog timer, and a parallel peripheral

interface (PPI).

BLACKFIN PROCESSOR PERIPHERALS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con-

tain a rich set of peripherals connected to the core via several

high bandwidth buses, providing flexibility in system configura-

tion as well as excellent overall system performance (see

Figure 1). The processors contain dedicated network communi-

cation modules and high speed serial and parallel ports, an

interrupt controller for flexible management of interrupts from

the on-chip peripherals or external sources, and power manage-

ment control functions to tailor the performance and power

characteristics of the processor and system to many application

scenarios.

All of the peripherals, except for the general-purpose I/O, CAN,

TWI, real-time clock, and timers, are supported by a flexible

DMA structure. There are also separate memory DMA channels

dedicated to data transfers between the processor’s various

memory spaces, including external SDRAM and asynchronous

memory. Multiple on-chip buses running at up to 133 MHz

provide enough bandwidth to keep the processor core running

along with activity on all of the on-chip and external

peripherals.

The Blackfin processors include an on-chip voltage regulator in

support of the processors’ dynamic power management capabil-

ity. The voltage regulator provides a range of core voltage levels

when supplied from V

DDEXT

. The voltage regulator can be

bypassed at the user’s discretion.

Table 1. Processor Comparison

Features

ADSP-BF534

ADSP-BF536

ADSP-BF537

Ethernet MAC — 1 1

CAN 1 1 1

TWI 1 1 1

SPORTs 2 2 2

UARTs 2 2 2

SPI 1 1 1

GP Timers 8 8 8

Watchdog Timers 1 1 1

RTC 1 1 1

Parallel Peripheral Interface 1 1 1

GPIOs 48 48 48

Memory

Configuration

L1 Instruction

SRAM/Cache

16K bytes 16K bytes 16K bytes

L1 Instruction

SRAM

48K bytes 48K bytes 48K bytes

L1 Data

SRAM/Cache

32K bytes 32K bytes 32K bytes

L1 Data SRAM 32K bytes — 32K bytes

L1 Scratchpad 4K bytes 4K bytes 4K bytes

L3 Boot ROM 2K bytes 2K bytes 2K bytes

Maximum Speed Grade 500 MHz 400 MHz 600 MHz

Package Options:

CSP_BGA

208-Ball

182-Ball

208-Ball

182-Ball

208-Ball

182-Ball

Rev. G | Page 4 of 68 | February 2009

ADSP-BF534/ADSP-BF536/ADSP-BF537

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

operands for compute operations come from the multiported

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2

multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates, and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

Figure 2. Blackfin Processor Core

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

8888

40 40

A0 A1

BARREL

SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ASTAT

40 40

32LD0

LD1

DAG0

DAG1

ADDRESS ARITHMETIC UNIT

DA1

DA0

PREG

RAB

TO MEMORY

ADSP-BF534/ADSP-BF536/ADSP-BF537

Rev. G | Page 5 of 68 | February 2009

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view

memory as a single unified 4G byte address space, using 32-bit

addresses. All resources, including internal memory, external

memory, and I/O control registers, occupy separate sections of

this common address space. The memory portions of this

address space are arranged in a hierarchical structure to provide

a good cost/performance balance of some very fast, low latency

on-chip memory as cache or SRAM, and larger, lower cost, and

performance off-chip memory systems. (See Figure 3).

The on-chip L1 memory system is the highest performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 516M bytes of

physical memory.

The memory DMA controller provides high bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external

memory spaces.

Internal (On-Chip) Memory

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have

three blocks of on-chip memory providing high-bandwidth

access to the core.

The first block is the L1 instruction memory, consisting of

64K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both cache and SRAM functional-

ity. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM, which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM, and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 512M bytes of SDRAM. A separate row can

be open for each SDRAM internal bank, and the SDRAM con-

troller supports up to 4 internal SDRAM banks, improving

overall performance.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks are only contiguous if each is fully populated

with 1M byte of memory.

I/O Memory Space

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do

not define a separate I/O space. All resources are mapped

through the flat 32-bit address space. On-chip I/O devices have

their control registers mapped into memory-mapped registers

(MMRs) at addresses near the top of the 4G byte address space.

These are separated into two smaller blocks, one which contains

the control MMRs for all core functions, and the other which

contains the registers needed for setup and control of the on-

chip peripherals outside of the core. The MMRs are accessible

only in supervisor mode and appear as reserved space to on-

chip peripherals.

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