A 240MHz Programmable Gain Amplifier & Filter
for Ultra Low Power Low-Rate UWB receivers
S. D' Amico', A. Baschirotto'<
'Dept, of Innovation Engineering-University of Salento
Leece, Italy
2Dept.
of
Physics -University
of
Milan-Bicocca
Milan - Italy
stefano.damico@unile.it
Abstract-
A 90nm-CMOS power-optimized Programmable
Gain Amplifier (PGA) for Ultra Low power Low Rate-Ultra
Wide Band (LR-UWB) receivers is illustrated. The PGA
features a 0-40dB programmable gain range with a 5dB gain-
step. In addition it implements a 6
th
-order
240MHz Bessel
lowpass
transfer
function . The cut-off frequency is about
constant, independently on the different gain settings. At
40dB gain, the input IdBcp is -44.8dBm, and the NF is
14.3dB. The
current
consumption (1.9mA at OdB-gain up to
2.9mA at 40dB-gain) is optimized by including the opamp
performance in the cell
transfer
function , and accordingly to
the selected gain level.
I. IN
TROD
UC
TIO
N
Low-Rate Ultra-Wide Band technology is an excellent
candidate for wireless sensors network applications. In
view
of
the low data rates in these applications, traditional
wireless radio architectures are sub-optimal, in particular in
term
of
power consumption, because
of
their complexity.
On the contrary, LR-UWB radios promise a very efficient
compromise between low power consumption, reliable
performance and low implementation complexity [1]-[2].
Radio communication will occur in the 3-10 GHz band,
offering a large channel bandwidth (up to 500MHz).
However, this broadband aspect makes the low-power
design
of
the baseband section very challenging. The
design
of
ultra-low power building blocks in advanced
CMOS technologies is mandatory [3]-[4]. In this paper, the
design
of
a baseband block merging Programmable Gain
Amplifier function and filter function is presented. This
block is embedded in a LR-UWB receiver, and exploits the
reduced dynamic range requirement by adopting an
aggressive implementation. The PGA&Filter block gain
and cut-off frequency are accurately controlled in order to
merge functionality and, then, improve implementation
efficiency. The overall PGA&Filter performs a 0-40dB
PGA and a 240M Hz 6
th-order
Bessel transfer function, as
978-1-4
244-4353-6
/09
/$
25
.00
©200 9
IEEE
K. Phili
ps
3, O. Rousseaux' , B. Gyselinckx'
3
IME
C-NL
Eindhoven- Netherland
required by digital communication. The experimental
results demonstrate the validity
of
the proposal.
The paper is organized as follows: after the introduction
in Section I, Section
II describes the PGA circuit schematic,
Section III shows the experimental results, Section IV
concludes the paper. The proposed PGA&Filter block will
be also called only PGA, for simplicity.
II. PGA
CIR
C
UI
T
SCH
EMATI
C
The proposed low-power PGA architecture is
implemented by means
of
the cascade
of
three gain cells
(Figure I). A wide bandwidth, high linearity output buffer
is added for measurements purpose only. The maximum
gain
of
the 1
5t
cell is IOdS, while the maximum gain
of
the
2
nd
and the 3
rd
cells is 15dB. The distribution
of
the gain
budget over the 3 stages is a trade-off between linearity
(lower gain for the
15
t stage, higher gain for the last stages)
and noise (higher gain for the
15t
stage, lower gain for the
last stages). The stages are AC coupled with 5pF and
biased with a 20kO resistor. This prevent problems with the
DC-offset for high gain modes.
..
-
--
------
--
.-.-
-- -- --
.---.-----.---
-- --
--.-
--
--.-----
--
------
-- --
--
-- -- --
--
-- -- --
------'1
..
!
~
~~
"
L;,~
'
tf
:
-y
-"~:~
Fa'
measurements
purpose only
Figure 1 - The PGA overall architecture
The structure
of
each cell is shown in Figure 2. Each
stage consists
of
an opamp with series-shunt feedback. The
closed loop de-gain is
k=(l +RI R
j
) .
With R
2
fixed, the value
of
R, is programmed to set the de-gain, This is obtained by
adding in parallel a full input stage (consisting
of
M
j
, R
j
,
and the PMOS current source).
OUTP
OUTN
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