AM335xdatasheet资源-CSDN下载

需积分: 9 7 浏览量 2015-10-13 10:44:32 上传评论收藏 4.24MB PDF 举报

资源推荐

资源详情

资源评论

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717F –OCTOBER 2011–REVISED APRIL 2013

Sitara™ AM335x ARM

Cortex™-A8 Microprocessors (MPUs)

Check for Samples: AM3359, AM3358

1 Device Summary

1.1 Features

1234567

– 32KB of L1 Data Cache with Single Error-

• Highlights

Detection (parity)

– Up to 1-GHz Sitara™ ARM

Cortex™-A8

– 256KB of L2 Cache with Error Correcting

32‑‑Bit RISC Microprocessor

Code (ECC)

• NEON™ SIMD Coprocessor

– 176KB of On-Chip Boot ROM

• 32KB of L1 Instruction and 32KB Data

– 64KB of Dedicated RAM

Cache with Single-Error Detection (parity)

– Emulation and Debug

• 256KB of L2 Cache with Error Correcting

Code (ECC) • JTAG

– mDDR(LPDDR), DDR2, DDR3, DDR3L – Interrupt Controller (up to 128 interrupt

Support requests)

– General-Purpose Memory Support (NAND, • On-Chip Memory (Shared L3 RAM)

NOR, SRAM) Supporting Up to 16-bit ECC

– 64 KB of General-Purpose On-Chip Memory

– SGX530 3D Graphics Engine Controller (OCMC) RAM

– LCD and Touchscreen Controller – Accessible to all Masters

– Programmable Real-Time Unit and Industrial – Supports Retention for Fast Wake-Up

Communication Subsystem (PRU-ICSS)

• External Memory Interfaces (EMIF)

– Real-Time Clock (RTC)

– mDDR(LPDDR), DDR2, DDR3, DDR3L

– Up to Two USB 2.0 High-Speed OTG Ports Controller:

with Integrated PHY

• mDDR: 200-MHz Clock (400-MHz Data

– 10, 100, 1000 Ethernet Switch Supporting Up Rate)

to Two Ports

• DDR2: 266-MHz Clock (532-MHz Data

– Serial Interfaces Including: Rate)

• Two Controller Area Network Ports (CAN) • DDR3: 400-MHz Clock (800-MHz Data

Rate)

• Six UARTs, Two McASPs, Two McSPI,

and Three I2C Ports • DDR3L: 400-MHz Clock (800-MHz Data

Rate)

– 12-Bit Successive Approximation Register

(SAR) ADC • 16-Bit Data Bus

– Up to Three 32-Bit Enhanced Capture • 1 GB of Total Addressable Space

Modules (eCAP)

• Supports One x16 or Two x8 Memory

– Up to Three Enhanced High-Resolution PWM Device Configurations

Modules (eHRPWM)

– General-Purpose Memory Controller (GPMC)

– Crypto Hardware Accelerators (AES, SHA,

• Flexible 8-Bit and 16-Bit Asynchronous

PKA, RNG)

Memory Interface with Up to seven Chip

Selects (NAND, NOR, Muxed-NOR, SRAM)

• MPU Subsystem • Uses BCH Code to Support 4-Bit, 8-Bit, or

16-Bit ECC

– Up to 1-GHz ARM

Cortex™-A8 32-Bit RISC

Microprocessor • Uses Hamming Code to Support 1-Bit

ECC

– NEON™ SIMD Coprocessor

– Error Locator Module (ELM)

– 32KB of L1 Instruction Cache with Single-

Error Detection (parity) • Used in Conjunction with the GPMC to

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Sitara, SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.

3Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.

4ARM is a registered trademark of ARM Ltd or its subsidiaries.

5EtherCAT is a registered trademark of EtherCAT Technology Group.

6POWERVR SGX is a trademark of Imagination Technologies Limited.

7All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

SPRS717F –OCTOBER 2011–REVISED APRIL 2013

www.ti.com

Locate Addresses of Data Errors from Week) and Time (Hours-Minutes-Seconds)

Syndrome Polynomials Generated Using Information

a BCH Algorithm

– Internal 32.768-kHz Oscillator, RTC Logic

• Supports 4-Bit, 8-Bit, and 16-Bit per 512- and 1.1-V Internal LDO

byte Block Error Location Based on BCH

– Independent Power-on-Reset

Algorithms

(RTC_PWRONRSTn) Input

• Programmable Real-Time Unit and Industrial

– Dedicated Input Pin (EXT_WAKEUP) for

Communication Subsystem (PRU-ICSS)

External Wake Events

– Supports protocols such as EtherCAT

– Programmable Alarm Can be Used to

PROFIBUS, PROFINET, EtherNet/IP™, and

Generate Internal Interrupts to the PRCM (for

Wake Up) or Cortex-A8 (for Event

– Peripherals Inside the PRU-ICSS Notification)

• One UART Port with Flow Control Pins, – Programmable Alarm Can be Used with

Supports Up to 12 Mbps External Output (PMIC_POWER_EN) to

Enable the Power Management IC to Restore

• Two MII Ethernet Ports that Support

Non-RTC Power Domains

Industrial Ethernet, such as EtherCAT

• Peripherals

• One MDIO Port

– Up to Two USB 2.0 High-Speed OTG Ports

• One Enhanced Capture (eCAP) Module

with Integrated PHY

• Power Reset and Clock Management (PRCM)

– Up to Two Industrial Gigabit Ethernet MACs

Module

(10, 100, 1000 Mbps)

– Controls the entry and Exit of Stand-By and

• Integrated Switch

Deep-Sleep Modes

• Each MAC Supports MII, RMII, RGMII and

– Responsible for Sleep Sequencing, Power

MDIO Interfaces

Domain Switch-Off Sequencing, Wake-Up

Sequencing and Power Domain Switch-On • Ethernet MACs and Switch Can Operate

Sequencing Independent of Other Functions

– Clocks • IEEE 1588v2 Precision Time Protocol

(PTP)

• Integrated 15-35 MHz High-Frequency

Oscillator Used to Generate a Reference – Up to Two Controller-Area Network (CAN)

Clock for Various System and Peripheral Ports

Clocks

• Supports CAN Version 2 Parts A and B

• Supports Individual Clock Enable and

– Up to Two Multichannel Audio Serial Ports

Disable Control for Subsystems and

(McASP)

Peripherals to Facilitate Reduced Power

• Transmit and Receive Clocks Up to 50

Consumption

MHz

• Five ADPLLs to Generate System Clocks

• Up to Four Serial Data Pins per McASP

(MPU Subsystem, DDR Interface, USB

Port with Independent TX and RX Clocks

and Peripherals [MMC and SD, UART,

• Supports Time Division Multiplexing

SPI, I2C], L3, L4, Ethernet, GFX [SGX530],

(TDM), Inter-IC Sound (I2S), and similar

LCD Pixel Clock)

Formats

– Power

• Supports Digital Audio Interface

• Two Non-Switchable Power Domains

Transmission (SPDIF, IEC60958-1, and

(Real-Time Clock [RTC], Wake-Up Logic

AES-3 Formats)

[WAKE-UP])

• FIFO Buffers for Transmit and Receive

• Three Switchable Power Domains (MPU

(256 bytes)

Subsystem [MPU], SGX530 [GFX],

– Up to Six UARTs

Peripherals and Infrastructure [PER])

• All UARTs Support IrDA and CIR Modes

• Implements SmartReflex™ Class 2B for

• All UARTs Support RTS and CTS Flow

Core Voltage Scaling Based On Die

Control

Temperature, Process Variation and

• UART1 Supports Full Modem control

Performance (Adaptive Voltage Scaling

– Up to Two Master and Slave McSPI Serial

[AVS])

Interfaces

• Dynamic Voltage Frequency Scaling

• Up to Two Chip Selects

(DVFS)

• Up to 48 MHz

• Real-Time Clock (RTC)

– Up to Three MMC, SD, and SDIO Ports

– Real-Time Date (Day-Month-Year-Day of

Submit Documentation Feedback

Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717F –OCTOBER 2011–REVISED APRIL 2013

• 1-Bit, 4-Bit and 8-Bit MMC, SD, and SDIO a Firmware Timer

Modes

• 512-Word Deep Internal FIFO

• MMCSD0 has dedicated Power Rail for

• Supported Display Types:

1.8-V or 3.3-V Operation

– Character Displays - Uses LCD

• Up to 48-MHz Data Transfer Rate

Interface Display Driver (LIDD)

• Supports Card Detect and Write Protect Controller to Program these Displays

• Complies with MMC4.3 and SD and SDIO – Passive Matrix LCD Displays - Uses

2.0 Specifications LCD Raster Display Controller to

Provide Timing and Data for Constant

– Up to Three I2C Master and Slave Interfaces

Graphics Refresh to a Passive Display

• Standard Mode (up to 100 kHz)

– Active Matrix LCD Displays - Uses

• Fast Mode (up to 400 kHz)

External Frame Buffer Space and the

– Up to Four Banks of General-Purpose IO

Internal DMA Engine to Drive

(GPIO)

Streaming Data to the Panel

• 32 GPIOs per Bank (Multiplexed with

– 12-Bit Successive Approximation Register

Other Functional Pins)

(SAR) ADC

• GPIOs Can be Used as Interrupt Inputs

• 200K Samples per Second

(Up to Two Interrupt Inputs per Bank)

• Input Can be Selected from any of the

– Up to Three External DMA Event Inputs That

Eight Analog Inputs Multiplexed Through

Can Also be Used as Interrupt Inputs

an 8:1 analog Switch

– Eight 32-Bit General-Purpose Timers

• Can be Configured to Operate as a 4-wire,

• DMTIMER1 is a 1-ms Timer Used for

5-wire, or 8-wire Resistive Touch Screen

Operating System (OS) Ticks

Controller (TSC) Interface

• DMTIMER4 - DMTIMER7 are Pinned Out

– Up to Three 32-Bit Enhanced Capture

– One Watchdog Timer

Modules (eCAP)

– SGX530 3D Graphics Engine

• Configurable as Three Capture Inputs or

• Tile-Based Architecture Delivering Up to

Three Auxiliary PWM Outputs

20 Million Polygons per second

– Up to Three Enhanced High-Resolution PWM

• Universal Scalable Shader Engine is a

Modules (eHRPWM)

Multi-Threaded Engine Incorporating

• Dedicated 16-Bit Time-Base Counter with

Pixel and Vertex Shader Functionality

Time and Frequency Controls

• Advanced Shader Feature Set in Excess

• Configurable as Six Single-Ended, Six

of Microsoft VS3.0, PS3.0 and OGL2.0

Dual-Edge Symmetric, or Three Dual-

• Industry Standard API Support of

Edge Asymmetric Outputs

Direct3D Mobile, OGL-ES 1.1 and 2.0,

– Up to Three 32-Bit Enhanced Quadrature

OpenVG 1.0, and OpenMax

Encoder Pulse (eQEP) Modules

• Fine-Grained Task Switching, Load

• Device Identification

Balancing and Power Management

– Contains Electrical fuse Farm (FuseFarm) of

• Advanced Geometry DMA Driven

Which Some Bits are Factory Programmable

Operation for Minimum CPU Interaction

• Production ID

• Programmable High-Quality Image Anti-

• Device Part Number (Unique JTAG ID)

Aliasing

• Device Revision (readable by Host ARM)

• Fully Virtualized Memory Addressing for

• Debug Interface Support

OS Operation in a Unified Memory

– JTAG and cJTAG for ARM (Cortex-A8 and

Architecture

PRCM), PRU-ICSS Debug

– LCD Controller

– Supports Device Boundary Scan

• Up to 24-Bits Data Output; 8-Bits per

– Supports IEEE 1500

Pixel (RGB)

• DMA

• Resolution Up to 2048x2048 (With

– On-Chip Enhanced DMA Controller (EDMA)

Maximum 126-MHz Pixel Clock)

has Three Third-Party Transfer Controllers

• Integrated LCD Interface Display Driver

(TPTC) and One Third-Party Channel

(LIDD) Controller

Controller (TPCC), Which Supports Up to 64

• Integrated Raster Controller

Programmable Logical Channels and Eight

• Integrated DMA Engine to Pull Data from

QDMA Channels. EDMA is Used for:

the External Frame Buffer without

• Transfers to and from On-Chip Memories

Burdening the Processor via Interrupts or

Submit Documentation Feedback

Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352

剩余235页未读，继续阅读

评论收藏

内容反馈

zhangshizhu1984

粉丝: 0

AM335x datasheet

最新资源

AM335x datasheet

AM335x DataSheet

AM335X datasheet

ti am335x datasheet

AM335X数据手册

AM335x Sitara Processors datasheet (Rev. K).pdf

am335x参考手册.pdf

TI AM335X Data Sheet

AM335x_ARM_Cortex-A8_MPU_DATASHEET

AM335x用户手册

AM335x Sitara Processors Technical Reference Manual.pdf

AM570x Sitara Processors datasheet.pdf

NXP TEF668X TEF6686 Full Datasheet 的完整数据手册

am335x for cortex-a8

amline的折线图操作代码

TPS65910电源管理芯片

飞思卡尔智能车主板+驱动板-电路方案

200余种常用芯片技术手册+常用电子元器选型（经典，必看）文档资料.zip

uboott移植实验手册及技术文档

TFT LCD 9320 驱动

串口助手工具合集.zip

TDMS转EXCEL官方插件

Vivado license 永久

STM32HAL库+RS485+串口+定时器+Modbus协议（主机+从机测试）

AD Type C 封装库 6Pin 24Pin分享（带3D视图）

STM32全系列 Keil MDK pack包（当前最新离线包）

张飞硬件1~20部+笔记完整版百度网盘链接.txt

Multisim创建LM386所需符号文件

I2C主机及从机Verilog代码实现.zip

usb连接232（usb-serial controller d驱动）

准确率（ACC)-错误率

讲清楚 Prompt, Agent, MCP 是什么

最新资源