[SPARC] Use op-then-neg instructions when we have VIS3 #135717

koachan · 2025-04-15T00:46:17Z

No description provided.

Created using spr 1.3.5

llvmbot · 2025-04-15T00:46:51Z

@llvm/pr-subscribers-backend-sparc

Author: Koakuma (koachan)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/135717.diff

2 Files Affected:

(modified) llvm/lib/Target/Sparc/SparcInstrVIS.td (+13)
(added) llvm/test/CodeGen/SPARC/float-vis3.ll (+59)

diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index b806f0c413899..27f8358576789 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -316,4 +316,17 @@ def : Pat<(i64 (sext (i32 (bitconvert f32:$src)))), (MOVSTOSW $src)>;
 def : Pat<(f32 (bitconvert i32:$src)), (MOVWTOS $src)>;
 def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>;
 def : Pat<(f64 (bitconvert i64:$src)), (MOVXTOD $src)>;
+
+// OP-then-neg FP operations.
+def : Pat<(f32 (fneg (fadd f32:$rs1, f32:$rs2))), (FNADDS $rs1, $rs2)>;
+def : Pat<(f64 (fneg (fadd f64:$rs1, f64:$rs2))), (FNADDD $rs1, $rs2)>;
+def : Pat<(f32 (fneg (fmul f32:$rs1, f32:$rs2))), (FNMULS $rs1, $rs2)>;
+def : Pat<(f32 (fmul (fneg f32:$rs1), f32:$rs2)), (FNMULS $rs1, $rs2)>;
+def : Pat<(f32 (fmul f32:$rs1, (fneg f32:$rs2))), (FNMULS $rs1, $rs2)>;
+def : Pat<(f64 (fneg (fmul f64:$rs1, f64:$rs2))), (FNMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul (fneg f64:$rs1), f64:$rs2)), (FNMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul f64:$rs1, (fneg f64:$rs2))), (FNMULD $rs1, $rs2)>;
+def : Pat<(f64 (fneg (fmul (fpextend f32:$rs1), (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul (fneg (fpextend f32:$rs1)), (fpextend f32:$rs2))), (FNSMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul (fpextend f32:$rs1), (fneg (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;
 } // Predicates = [HasVIS3]
diff --git a/llvm/test/CodeGen/SPARC/float-vis3.ll b/llvm/test/CodeGen/SPARC/float-vis3.ll
new file mode 100644
index 0000000000000..bc9904dfa356a
--- /dev/null
+++ b/llvm/test/CodeGen/SPARC/float-vis3.ll
@@ -0,0 +1,59 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=sparc64 -mattr=+vis3 < %s | FileCheck %s
+
+define float @fnadds(float %a, float %b) nounwind {
+; CHECK-LABEL: fnadds:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    retl
+; CHECK-NEXT:    fnadds %f1, %f3, %f0
+entry:
+  %add = fadd float %a, %b
+  %fneg = fneg float %add
+  ret float %fneg
+}
+
+define double @fnaddd(double %a, double %b) nounwind {
+; CHECK-LABEL: fnaddd:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    retl
+; CHECK-NEXT:    fnaddd %f0, %f2, %f0
+entry:
+  %add = fadd double %a, %b
+  %fneg = fneg double %add
+  ret double %fneg
+}
+
+define float @fnmuls(float %a, float %b) nounwind {
+; CHECK-LABEL: fnmuls:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    retl
+; CHECK-NEXT:    fnmuls %f1, %f3, %f0
+entry:
+  %mul = fmul float %a, %b
+  %fneg = fneg float %mul
+  ret float %fneg
+}
+
+define double @fnmuld(double %a, double %b) nounwind {
+; CHECK-LABEL: fnmuld:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    retl
+; CHECK-NEXT:    fnmuld %f0, %f2, %f0
+entry:
+  %mul = fmul double %a, %b
+  %fneg = fneg double %mul
+  ret double %fneg
+}
+
+define double @fnsmuld(float %a, float %b) nounwind {
+; CHECK-LABEL: fnsmuld:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    retl
+; CHECK-NEXT:    fnsmuld %f1, %f3, %f0
+entry:
+  %conv.i = fpext float %a to double
+  %conv1.i = fpext float %b to double
+  %mul = fmul double %conv.i, %conv1.i
+  %fneg = fneg double %mul
+  ret double %fneg
+}

koachan · 2025-04-15T00:55:08Z

llvm/lib/Target/Sparc/SparcInstrVIS.td

+def : Pat<(f32 (fneg (fadd f32:$rs1, f32:$rs2))), (FNADDS $rs1, $rs2)>;
+def : Pat<(f64 (fneg (fadd f64:$rs1, f64:$rs2))), (FNADDD $rs1, $rs2)>;
+def : Pat<(f32 (fneg (fmul f32:$rs1, f32:$rs2))), (FNMULS $rs1, $rs2)>;
+def : Pat<(f32 (fmul (fneg f32:$rs1), f32:$rs2)), (FNMULS $rs1, $rs2)>;
+def : Pat<(f32 (fmul f32:$rs1, (fneg f32:$rs2))), (FNMULS $rs1, $rs2)>;
+def : Pat<(f64 (fneg (fmul f64:$rs1, f64:$rs2))), (FNMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul (fneg f64:$rs1), f64:$rs2)), (FNMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul f64:$rs1, (fneg f64:$rs2))), (FNMULD $rs1, $rs2)>;
+def : Pat<(f64 (fneg (fmul (fpextend f32:$rs1), (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul (fneg (fpextend f32:$rs1)), (fpextend f32:$rs2))), (FNSMULD $rs1, $rs2)>;
+def : Pat<(f64 (fmul (fpextend f32:$rs1), (fneg (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;


A question: is there any sort of canonical form for which -(rs1*rs2)-type expressions will be converted to?
It feels excessive to have to list variants of it in this way.

I have little experience with floating point support in ISel yet. Maybe @arsenm can help here

fneg/fabs modifier folding is complex. We have both uses-into-defs and defs-into-uses patterns. The generic code has a conservative subset of foldable cases handled in getNegatedExpression, mostly dependent on what isFNegFree/isFAbsFree report. On AMDGPU we have a much more aggressive set of context dependent folds.

In general these are pushed up into the defs

I don't think the backend tries to do anything fancy with FP, so probably it just passes expressions through getNegatedExpression.
That being said, on a quick reading of it:

-(a+b) can be turned into -a-b or -b-a, but only if we don't care about signed zeros.

-(a*b) will (?) be turned into -a*b or a*-b.

So I guess for multiplies I only need to handle the -a*b and a*-b variants, but for addition... is there a way to enable a pattern conditionally on Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()?

You can write a pattern that checks the flags, but my broader point would be you should probably be implementing isFNegFree so all the default logic works

Hmm, I see that isFNegFree only passes the type of the value, I'm not sure how to check for it.
In this case I care less about types (it works for f32 and f64 equally well) and more about expressions (it's only free in the very specific cases of -(a+b) and -(a*b)). Is it still possible to do that?

I see that implementing isFNegFree makes it so that expressions involving negation doesn't get rewritten, thanks.

Created using spr 1.3.5

arsenm · 2025-04-17T11:36:23Z

llvm/test/CodeGen/SPARC/float-vis3.ll

+  %mul = fmul double %conv.i, %conv1.i
+  %fneg = fneg double %mul
+  ret double %fneg
+}


This set of tests doesn't look like it covers all the patterns here. Should you also cover vectors to see these patterns still work after scalarization?

I added some tests for other patterns and vectors, is that enough?

It's hard to verify test coverage when so much is in one patch, I would have done this one pattern per patch with precommitted tests so it's trivial to see that it's tested

Created using spr 1.3.5

koachan · 2025-04-26T23:02:12Z

Hmm, changing my approach here.
To make the patch much simpler, instead of trying to handle every combination of operations, this one will only handle the basic cases of literal -(a+b) and -(a*b).
Handling other equivalent patterns will be done in separate patches in the future.

koachan · 2025-05-03T13:58:33Z

Ping?

arsenm

Not sure isFNegFree is doing anything in this patch, would be best to drop it and separately test the combines it enables

arsenm · 2025-05-05T08:50:16Z

llvm/lib/Target/Sparc/SparcISelLowering.cpp

+bool SparcTargetLowering::isFNegFree(EVT VT) const {
+  if (Subtarget->isVIS3())
+    return VT == MVT::f32 || VT == MVT::f64;
+  return false;
+}


This ideally would be completely separate patch from the patterns. This enables independent combines

koachan · 2025-05-05T15:10:06Z

Not sure isFNegFree is doing anything in this patch, would be best to drop it and separately test the combines it enables

It prevents the multiplication tests from being rewritten into a*-b, a pattern that we currently don't handle.
Without it, the codegen wouldn't issue fnmuls/fnmuls/fnsmuld instructions.

koachan · 2025-05-05T22:26:37Z

Wait did this get hand-merged? This PR was made by spr and I thing that made the commit landed in the wrong place, ahah~

koachan · 2025-05-05T22:36:59Z

In any case, manually merged it just now.

arsenm · 2025-05-06T18:40:55Z

I just hit the button. This also doesn't have the SPR generated comments in the description

[𝘀𝗽𝗿] initial version

2dfb6f0

Created using spr 1.3.5

llvmbot added the backend:Sparc label Apr 15, 2025

koachan requested review from brad0, rorth and s-barannikov April 15, 2025 00:52

koachan commented Apr 15, 2025

View reviewed changes

s-barannikov requested a review from arsenm April 15, 2025 01:47

Rebase & update

31d86de

Created using spr 1.3.5

arsenm reviewed Apr 17, 2025

View reviewed changes

Add tests for other patterns and vectors

d4d9827

Created using spr 1.3.5

brad0 requested a review from arsenm April 20, 2025 04:44

Rebase and reduce scope to handle only literal -(a+b) and -(a*b)

78d08ff

Created using spr 1.3.5

arsenm approved these changes May 5, 2025

View reviewed changes

arsenm merged commit 6bedda9 into users/koachan/spr/main.sparc-use-op-then-neg-instructions-when-we-have-vis3 May 5, 2025
14 of 17 checks passed

arsenm deleted the users/koachan/spr/sparc-use-op-then-neg-instructions-when-we-have-vis3 branch May 5, 2025 19:02

koachan restored the users/koachan/spr/sparc-use-op-then-neg-instructions-when-we-have-vis3 branch May 5, 2025 22:26

koachan mentioned this pull request May 5, 2025

[SPARC] Use op-then-neg instructions when we have VIS3 #138603

Merged

koachan deleted the users/koachan/spr/sparc-use-op-then-neg-instructions-when-we-have-vis3 branch May 5, 2025 22:36

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[SPARC] Use op-then-neg instructions when we have VIS3 #135717

[SPARC] Use op-then-neg instructions when we have VIS3 #135717

koachan commented Apr 15, 2025

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[SPARC] Use op-then-neg instructions when we have VIS3 #135717

[SPARC] Use op-then-neg instructions when we have VIS3 #135717

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