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Assignment 1: 8 Bit Ring Counter

This document describes the design of an 8-bit ring counter. It includes an introduction to ring counters, the counting sequence of an 8-bit ring counter, VHDL code for a behavioral model, an RTL schematic, and simulation results. It also includes structural VHDL code that implements the counter using D flip-flops and their interconnections.

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Aarohi Vora
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63 views

Assignment 1: 8 Bit Ring Counter

This document describes the design of an 8-bit ring counter. It includes an introduction to ring counters, the counting sequence of an 8-bit ring counter, VHDL code for a behavioral model, an RTL schematic, and simulation results. It also includes structural VHDL code that implements the counter using D flip-flops and their interconnections.

Uploaded by

Aarohi Vora
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ASSIGNMENT 1

8 Bit Ring Counter

SUBJECT: ASIC DESIGN SUBMITTED TO: PROF.NEHAL SHAH PREPARED BY: AAROHI VORA ROLL NO. 1216 CLASS: ME 1st SEM

INTRODUCTION
A ring counter is a digital circuit which consists of a series of flip flops connected together in a feedback manner. The circuit is special type of shift register where the output of the last flipflop is fed back to the input of first flipflop. When the circuit is reset, except one of the flipflop output,all others are made zero.

8 bit ring counter using D flip flop:

Counting sequence of a ring counter:

VHDL BEHAVIORAL CODE FOR 8 Bit Ring Counter


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity t1 is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (7 downto 0)); end t1; architecture Behavioral of t1 is signal temp:std_logic_vector(7 downto 0); begin process(rst,clk) begin if(rst='1')then temp<= (0=> '1', others =>'0'); elsif(clk'event and clk='1')then temp(1)<=temp(0); temp(2)<=temp(1); temp(3)<=temp(2); temp(4)<=temp(3); temp(5)<=temp(4); temp(6)<=temp(5); temp(7)<=temp(6); temp(0)<=temp(7); end if; end process; q<=temp; end Behavioral;

RTL Schematic

SIMULATION RESULTS:

Structural code for 8 bit ring counter


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity t3 is Port ( CLK : in STD_LOGIC; rst : in STD_LOGIC; count : out STD_LOGIC_VECTOR (7 downto 0)); end t3; architecture Behavioral of t3 is COMPONENT t2struct PORT( rst : IN std_logic; clk : IN std_logic; d : IN std_logic; q : OUT std_logic ); END COMPONENT; signal temp:std_logic_vector(7 downto 0):=(0=> '1', others =>'0'); begin I1: t2struct PORT MAP( rst =>rst , clk =>CLK , q =>temp(0) , d =>temp(7) );

Continued
I2: t2struct PORT MAP( rst =>rst , clk =>CLK , q =>temp(1) , d =>temp(0) ); I3: t2struct PORT MAP( rst =>rst , clk =>CLK , q =>temp(2) , d =>temp(1) ); I4: t2struct PORT MAP( rst =>rst , clk =>CLK , q =>temp(3) , d =>temp(2) ); I5: t2struct PORT MAP( rst =>rst , clk =>CLK , q =>temp(4) , d =>temp(3) ); I6: t2struct PORT MAP( rst =>rst , clk =>CLK , q =>temp(5) , d =>temp(4) );

Continued

I7: t2struct PORT MAP(

rst =>rst , clk =>CLK , q =>temp(6) , d =>temp(5)


); I8: t2struct PORT MAP( rst =>rst , clk =>CLK , q =>temp(7) , d =>temp(6) ); count<=temp; end Behavioral;

RTL Schematic:

Simulation Results:

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