DESIGN AND ANALYSIS OF 4Kb SRAM ARRAY CELL FOR THE DEVELOPMENT OF SRAM CHIP

G.HARISH KUMAR1, M.ROHIT KUMAR2, M.S.CHANDRA SEKHAR3, HARISH.M.KITTUR4

Abstract: As the electronic applications get faster and faster, the need for large quantities of data at very high speeds increases. As the micro processor speed increases, cache memory plays a vital role in accomplishing data. Out of these SRAM is preferred by most of the companies to develop their products due to its own advantages such as high speed, low power, and non destructive readout & of low cost. In this paper we deal with SRAM architecture and its design. We present SRAM memory array cells of size 4Kb with a frequency of 20GHz in 180nm technology with modified write driver circuit and results are simulated with Mentor Graphics using ELDONET simulator.
Keywords- SRAM Array, Write driver, Cell Architecture, peripheral circuitry

INTRODUCTION Static Random Access Memory known as SRAM is used to store single Bit data temporarily. The basic SRAM cell as shown in Fig(1) is designed with six transistors, out of which two are pull up transistors and two pull down transistors, are connected back to back as two invertors connected back to back ,with two access transistors (pass gates) which are used to store the data at specified address controlled by WL pins.

Initially during Read operation the Bit and Bit line bars shown in the Fig are in high impedance state and to maintain this state we use Precharge circuit. This Precharge circuit alters the voltage levels of the Bit line and its complement line specified by another circuit called Half VDD Voltage Generator. The state of SRAM cell can be observed through Sense Amplifier which senses the value at SRAM cell through Bit line and Bit line bar and gives an output. The major periphery circuit involved in the total SRAM architecture is the Isolation circuit which plays a major role in case of delay characteristics of Sense Amplifier because the cells acts as a load on Sense Amplifier, so Isolation circuit is used to isolate the unused or unwanted cells from the column. The efficiency of output not only depends on cell characteristics but also on performance of peripheral circuitry. In this paper we concentrate on initial stage of SRAM architecture that is Write Driver circuit that we discuss in fore coming section.

The rest of this article is sectioned as follows. In section 2 we discuss the concept of basic SRAM cell operation and its peripheral circuitry. In section 3.we observe the problems and corresponding rectifications of write driver circuit. In section 4 Design rules of SRAM cell and its peripheral circuitry are discussed. In section 5 we implemented the 4Kb SRAM array cell architecture. In section 6 we observe the comparative results of write driver circuit and SRAM cell execution result are displayed. CONCEPT OF SRAM CELL The SRAM operates in two different modes. They are: 1) Write mode & 2) Read mode.

Fig (1). Basic cell structure of SRAM

In Read Mode: A Read operation is initiated by pre-charging both Bit Line and Bit Line bar to logic 1. Word Line is set high to close NMOS pass transistors to push the contents stored in the cell on the Bit Line and Bit Line. In write mode: A write operation is initiated by pre-charging Bit Line to 1 and making Bit Line bar to logic 0. Word Line is set high to close NMOS pass transistors to push the contents stored in the cell on the Bit Line and Bit Line. To determine the functionality of SRAM cell, we need write driver, Precharge, Sense Amplifier and Isolation circuit. Let us discuss the functionality of each and every component and complete circuit diagram is shown in Fig (2). Write driver The write driver circuit has two input pins (one is enable and other is data pin) and two output pins (one is Bit and other is Bit line bar). The read and write mode of operation is selected by an enable pin of write driver circuitry. If the enable pin is 1 then driver circuit places the value on Bit line and its complement on Bit line bar which is available at data pins. If the enable pin is 0 then driver maintain high impedance state on both Bit and Bit line bar. Isolation The two transistors of Isolation circuitry are used for Isolation and remaining one is used to avoid the capacitive coupling between two lines. This circuit has one input pin called ISO pin. If ISO pin is 0 which is used to isolate

the total column of cell from Sense Amplifier in write mode. Main use of Isolation is reducing the load on reading element. Precharge: The Precharge circuitry consists of three transistors in which two are used for Precharge the Bit lines to a specified voltage level and remaining one is used to avoid the capacitive coupling between two lines. If Precharge pin is0 the both lines are charged. Sense amplifer Due to large arrays of SRAM cells, the resulting signal, in the event of a Read operation, has a much lower voltage swing. To amplify that swing to a well defined state (i.e.) either 0 or 1 a Sense Amplifier is used to amplify voltage coming off Bit Line and Bit Line bar. The voltage coming out of the Sense Amplifier typically has a fully swing (0 - VDD) voltage. Sense Amplifier also helps to reduce the delay and power dissipation in the overall SRAM chip.

Fig (2). SRAM cell with pheripheral circuitary

PROBLEMS WITH THE WRITE DRIVER & SOLUTION The need of Write Driver circuit is to place the Bit value on Bit line and Bit line bar corresponding to the Enable and Data inputs. This is because these inputs are used to select the mode of operation performed on the SRAM cell. So our aim is to design the Write Driver circuit that must be free from errors.

The traditional and symmetrical circuitry of Write Driver is shown in Fig (3) is not functioning well for read operation mode, but we need to maintain high impedance on Bit line and Bit line bar so we move to Precharge circuit to charge the lines to cover the problem of write driver. Here we use 13 transistors to design the Write

Driver with Precharge circuitry. We use another circuitry called half voltage generator to perform better functionality.

We propose the modification in write driver circuitry shown in Fig (4) with 10 transistors to perform similar operation of traditional Writer Driver with Precharge circuit and the main advantage of this circuit is to avoid the Precharge pin for whole circuit. Due to this area of total architecture can be minimized by 4-6%.

Fig (3). Traditional write driver circuit

Fig (4). Modified writer driver circuit

The modification can be taken by considering the functionality of driver circuit and implement in boolean form with out any changes or any deviations in the actual operation.
DESIGN RULES OF SRAM CELL AND ITS PHERIPHERALS

Now a days MOS technology plays a major role to design any analog circuitry, so the major discussion that we concentrate on dimension parameters corresponding to the technology and to care about the frequency of input signals to perform the better functionally because the design needs some time to process the inputs. In case of SRAM cell a) Minimum size transistors are chosen for pass gates to fast access and for quick react to the word line.

b) NMOS transistors of back to back connected invertors are sized larger than pass gates to avoid read setup problem and

c) PMOS transistors of back to back connected invertors are smaller for successful write. In Case Of Isolation We use PMOS transistors for the design of Isolation, it has less mobility charge carrier and response time is low (we need to give high voltage with certain period of time). So the width should be taken considerably low for quick response. In Case Of Sense Amplifer The NMOS transistor used as gating device between Sense Amplifier and ground terminal. So threshold voltage of gated transistor must be high for avoiding leakages, due to this reason the width of gated transistor should be larger. The transistors sizing of Write Driver circuits can be made by considering the RC delay model. Timing rules Initially the Word line should be OFF for certain period of time before the read operation is performed because if Word line is made high from starting of read operation, the access transistors (pass gates) will be turned ON and direct discharge path will be created. Hence it will not recognize the status of cell properly due to the degrade in the voltage levels of Bit line and Bit line bar.

Precharge should be OFF after word line becomes high in read operation. The Isolation should be ON before activating the SSA pin because the PMOS should give stable operation.

SSA pin should be OFF until the stable values are obtained on the Bit line and Bit line bar. 4Kb SRAM ARRAY ARCHITECTURE We know that any kind of array can be defined in the matrix form. Similarly in SRAM array , we place the cells in every cross-point of column and row lines to get a matrix fashion. In case the large size of array, it is impossible to define the 2n address lines because the design of decoder is a difficult task to serve the corresponding address to the input address vector so we use to divide large size into no. of partitions to define small sizes called banks and again perform sub-partitions (shown in Fig (5)) from the partition block until the bank size gets reduced to built as normal array fashion. Here the input address vector is divided into no. of subsets based on partition value and this subset of input vector is used to give the every partition decoder. The first partition decoder output is used to enable the second stage decoders; this decoder output can enable the third stage decoders and so on until the particular row is selected.

Fig (5): 128Bit SRAM array (one subpartition bank in 4Kb array)

Fig (6): 4Kb SRAM array cell architecture

RESULTS

Gra ph (1): Result for SRAM with traditional write driver Graph (2): Result for SRAM with modified write driver

Graph (3): result for single cell with modified write driver

CONCLUSION

In this paper we have successfully modified the write driver circuit to eliminate distortions or deviations from the operation. The design of array architecture is subdivided into various sizes of partitions to reduce the complexity of large size of decoder. The cell and architecture are designed with the modified Write Driver circuit and is simulated with the Mentor Graphics in 180nm technology using ELDONET simulator. References
[1]

HIGH PERFORMANCE MEMORY TESTING :: Design principles, Fault modeling and self-test by R.Dean Adams IBM. Springer/2005-10-30/ISBN:1402072554/PDF.

[2]

Zhao Huizhuo and Xu Bingshi Design of three important pheripheral circuits of SRAM based on 9T cell 978-1-4244-4669-8/09/2009 IEEE

[3] [4]

1Kbyte SRAM chip Prototype Report http:// www.cedcc.psu.edu/ khanjan/ vlsiprot.htm Design of a 32*64 SRAM bwrc.eecs.berkeley.edu /classes/ icdesign /ee141.../EE141-Proj1.pdf