Date: October 21, 2012

Tri_Pipe.vhd

Project: Tri_Pipe

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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Tri_Pipe is port( Clock : Reset_N : InDataReady : A, B, C : OutDataReady: Y : ); end entity Tri_Pipe;

in in in in out out

std_logic; std_logic; std_logic; std_logic_vector(7 downto 0); std_logic; std_logic_vector(15 downto 0)

architecture RTL of Tri_Pipe is signal signal signal signal signal signal signal signal signal signal signal begin CONTROL_PATH : process(Clock, Reset_N) begin if (Reset_N = '0') then InDataReady_Delay <= '0'; EnA <= '1'; -- So tri-state bus has a drive. EnB <= '0'; EnC <= '0'; EnA_Delay <= '0'; elsif rising_edge(Clock) then InDataReady_Delay <= InDataReady; EnA <= InDataReady or ((not InDataReady_Delay) and (not EnB)); EnB <= InDataReady_Delay; EnC <= EnB; EnA_Delay <= EnC; end if; end process CONTROL_PATH; OutDataReady <= EnC; IP_BUS_REG: process(Clock) begin if rising_edge(Clock) then A_Hold <= A; B_Hold <= B; C_Hold <= C; A_Delay <= A_Hold;
Page 1 of 2 Revision: Tri_Pipe

InDataReady_Delay : std_logic; EnA, EnB, EnC : std_logic; EnA_Delay : std_logic; A_Hold : std_logic_vector(7 downto 0); B_Hold : std_logic_vector(7 downto 0); C_Hold : std_logic_vector(7 downto 0); A_Delay : std_logic_vector(7 downto 0); M : std_logic_vector(7 downto 0); M_Delay : std_logic_vector(7 downto 0); Multin : std_logic_vector(7 downto 0); result : std_logic_vector(15 downto 0);

Date: October 21, 2012

Tri_Pipe.vhd

Project: Tri_Pipe

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M_Delay <= M; Y <= result; end if; end process IP_BUS_REG; -- Tri-state bus M <= A_Hold when M <= B_Hold when M <= C_Hold when drivers EnA = '1' else (others => 'Z'); EnB = '1' else (others => 'Z'); EnC = '1' else (others => 'Z');

Multin <= A_Delay when EnA_Delay = '1' else M; process (M_Delay, Multin) variable product : std_logic_vector(15 downto 0); variable temp : std_logic_vector(15 downto 0); variable zeros : std_logic_vector(7 downto 0); begin product := (others => '0'); zeros := (others => '0'); temp := (others => '0'); for i in 0 to 7 loop if M_Delay(i) = '1' then temp := zeros(7 downto i) & Multin & zeros(i-1 downto 0); else temp := (others => '0'); end if; product := product + temp; end loop; result <= product; end process; end RTL;

Page 2 of 2

Revision: Tri_Pipe

Date: October 21, 2012

HIER_FSMS_CONTROLPATH.vhd

Project: TP2

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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity HIER_FSMS_CONTROLPATH is port( Clock, Reset, ThreeOnly : FirstDataInRdy : En_A, En_B, En_C, En_D : Mux1_Sel, Mux2_Sel : En_AB, En_AC, En_AD : En_BC, En_BD, En_CD : Mux3_Sel : FirstDataOutRdy : ); end entity HIER_FSMS_CONTROLPATH;

in in out out out out out

std_logic; std_logic; out std_logic; integer range 0 to 2; std_logic; std_logic; integer range 0 to 3; std_logic

architecture RTL of HIER_FSMS_CONTROLPATH is type StateTypeMasterFSM is (ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, ST8, ST9, ST10, ST11, ST12); type StateTypeFSM1 is (ST_A, ST_B, ST_C, ST_D); type StateTypeFSM2 is (Zero, One, Two, Three, Four, Five); type StateTypeFSM3 is (ST_Sum1, ST_Sum2, ST_Sum3, ST_NoSum); signal signal signal signal CurrStateMasterFSM, NextStateMasterFSM : StateTypeMasterFSM; CurrStateFSM1, NextStateFSM1 : StateTypeFSM1; CurrStateFSM2, NextStateFSM2 : StateTypeFSM2; CurrStateFSM3, NextStateFSM3 : StateTypeFSM3;

signal StartFSM1, StartFSM2, StartFSM3 : std_logic; begin --------------------- Master FSM -------------------MASTER_FSM_COMB : process(FirstDataInRdy, ThreeOnly, CurrStateMasterFSM) begin StartFSM1 <= '0'; StartFSM2 <= '0'; StartFSM3 <= '0'; FirstDataOutRdy <= '0'; case (CurrStateMasterFSM) is when ST0 => if (FirstDataInRdy = '1') then StartFSM1 <= '1'; if (ThreeOnly = '1') then NextStateMasterFSM <= ST7; else NextStateMasterFSM <= ST1; end if; else NextStateMasterFSM <= ST0; end if;
Page 1 of 5 Revision: TP2

Date: October 21, 2012

HIER_FSMS_CONTROLPATH.vhd

Project: TP2

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when ST1 => NextStateMasterFSM <= ST2; when ST2 => StartFSM2 <= '1'; NextStateMasterFSM <= ST0; when ST3 => NextStateMasterFSM <= ST4; when ST4 => NextStateMasterFSM <= ST5; when ST5 => NextStateMasterFSM <= ST6; when ST6 => StartFSM3 <= '1'; FirstDataOutRdy <= '1'; if (FirstDataInRdy = '1') then StartFSM1 <= '1'; NextStateMasterFSM <= ST1; else NextStateMasterFSM <= ST0; end if; when ST7 => NextStateMasterFSM <= ST8; when ST8 => StartFSM2 <= '1'; NextStateMasterFSM <= ST9; when ST9 => if (FirstDataInRdy = '1') then StartFSM1 <= '1'; NextStateMasterFSM <= ST10; else NextStateMasterFSM <= ST12; end if; when ST10 => StartFSM3 <= '1'; FirstDataOutRdy <= '1'; NextStateMasterFSM <= ST11; when ST11 => StartFSM2 <= '1'; NextStateMasterFSM <= ST9; when ST12 => StartFSM3 <= '1'; FirstDataOutRdy <= '1'; NextStateMasterFSM <= ST0; when others => NextStateMasterFSM <= ST0; end case; end process MASTER_FSM_COMB; MASTER_FSM_SEQ : process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then CurrStateMasterFSM <= ST0; else CurrStateMasterFSM <= NextStateMasterFSM; end if; end if; end process MASTER_FSM_SEQ; ---------- FSM1 --------FSM1_COMB : begin En_A <= En_B <= En_C <= En_D <= process(StartFSM1, ThreeOnly, CurrStateFSM1) '0'; '0'; '0'; '0';
Page 2 of 5 Revision: TP2

Date: October 21, 2012

HIER_FSMS_CONTROLPATH.vhd

Project: TP2

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case (CurrStateFSM1) is when ST_A => if (StartFSM1 = '1') then NextStateFSM1 <= ST_B; En_A <= '1'; else NextStateFSM1 <= ST_A; end if; when ST_B => NextStateFSM1 <= ST_C; En_B <= '1'; if (ThreeOnly = '1') then NextStateFSM1 <= ST_A; En_A <= '1'; else NextStateFSM1 <= ST_D; end if; En_C <= '1'; NextStateFSM1 <= ST_A; En_D <= '1';

when ST_C =>

when ST_D =>

when others => NextStateFSM1 <= ST_A; end case; end process FSM1_COMB; FSM1_SEQ : process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then CurrStateFSM1 <= ST_A; else CurrStateFSM1 <= NextStateFSM1; end if; end if; end process FSM1_SEQ;

---------- FSM2 --------FSM2_COMB : process(StartFSM2, ThreeOnly, CurrStateFSM2) begin Mux1_Sel <= 0; Mux2_Sel <= 0; En_AB <= '0'; En_AC <= '0'; En_AD <= '0'; En_BC <= '0'; En_BD <= '0'; En_CD <= '0'; case (CurrStateFSM2) is when Zero => if (StartFSM2 = '1') then En_AB <= '1'; NextStateFSM2 <= One;
Page 3 of 5 Revision: TP2

Date: October 21, 2012

HIER_FSMS_CONTROLPATH.vhd

Project: TP2

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else NextStateFSM2 <= Zero; end if; Mux1_Sel <= 0; Mux2_Sel <= 0; when One => Mux1_Sel <= 0; Mux2_Sel <= 1; En_AC <= '1'; if (ThreeOnly = '1') then NextStateFSM2 <= Three; else NextStateFSM2 <= Two; end if; Mux1_Sel <= 0; Mux2_Sel <= 2; En_AD <= '1'; NextStateFSM2 <= Three; Mux1_Sel <= 1; Mux2_Sel <= 1; En_BC <= '1'; if (ThreeOnly = '1') then NextStateFSM2 <= Zero; else NextStateFSM2 <= Four; end if; Mux1_Sel <= 1; Mux2_Sel <= 2; En_BD <= '1'; NextStateFSM2 <= Five; Mux1_Sel <= 0; Mux2_Sel <= 2; En_CD <= '1'; NextStateFSM2 <= Zero;

when Two =>

when Three =>

when Four =>

when Five =>

when others => NextStateFSM2 <= Zero; end case; end process FSM2_COMB; FSM2_SEQ : process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then CurrStateFSM2 <= Zero; else CurrStateFSM2 <= NextStateFSM2; end if; end if; end process FSM2_SEQ; ---------- FSM3 --------Page 4 of 5 Revision: TP2

Date: October 21, 2012

HIER_FSMS_CONTROLPATH.vhd

Project: TP2

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FSM3_COMB : process(StartFSM3, ThreeOnly, CurrStateFSM3) begin Mux3_Sel <= 0; case (CurrStateFSM3) is when ST_Sum1 => Mux3_Sel <= 0; if (StartFSM3 = '1') then if (ThreeOnly ='1') then NextStateFSM3 <= ST_NoSum; else NextStateFSM3 <= ST_Sum2; end if; else NextStateFSM3 <= ST_Sum1; end if; when ST_Sum2 => Mux3_Sel <= 1; NextStateFSM3 <= ST_Sum3; when ST_Sum3 => Mux3_Sel <= 2; NextStateFSM3 <= ST_Sum1; when ST_NoSum => Mux3_Sel <= 3; NextStateFSM3 <= ST_Sum1; when others => end case; end process FSM3_COMB; NextStateFSM3 <= ST_Sum1;

FSM3_SEQ : process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then CurrStateFSM3 <= ST_Sum1; else CurrStateFSM3 <= NextStateFSM3; end if; end if; end process FSM3_SEQ; end architecture RTL;

Page 5 of 5

Revision: TP2

Date: October 21, 2012

HIER_FSMS_DATAPATH.vhd

Project: TP2

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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity HIER_FSMS_DATAPATH is port( Clock : En_A, En_B, En_C, En_D : Mux1_Sel, Mux2_Sel : En_AB, En_AC, En_AD : En_BC, En_BD, En_CD : Mux3_Sel : SerialIn : SerialOut : ); end entity HIER_FSMS_DATAPATH;

in

std_logic; in std_logic; in integer range 0 to 2; in std_logic; in std_logic; in integer range 0 to 3; in integer range 0 to 15; out integer range 0 to 511

architecture RTL of HIER_FSMS_DATAPATH is signal signal signal signal signal begin A, B, C, D : integer range 0 to 15; Mult1, Mult2 : integer range 0 to 15; Mult : integer range 0 to 255; AB, AC, AD, BC, BD, CD : integer range 0 to 255; Sum1, Sum2, Sum3, NoSum : integer range 0 to 511;

----------------------------------------- Datapath stage 1 controlled by FSM1 ---------------------------------------STAGE1 : process(Clock) begin if rising_edge(Clock) then if (En_A = '1') then A if (En_B = '1') then B if (En_C = '1') then C if (En_D = '1') then D end if; end process STAGE1;

<= <= <= <=

SerialIn; SerialIn; SerialIn; SerialIn;

end end end end

if; if; if; if;

----------------------------------------- Datapath stage 2 controlled by FSM2 ---------------------------------------STAGE2 : process(Clock, Mux1_Sel, Mux2_Sel) begin case (Mux1_Sel) is when 0 => Mult1 <= A; when 1 => Mult1 <= B; when 2 => Mult1 <= C; when others => Mult1 <= A; end case; case (Mux2_Sel) is when 0 => Mult2 <= B; when 1 => Mult2 <= C; when 2 => Mult2 <= D; when others => Mult2 <= B; end case;
Page 1 of 2 Revision: TP2

Date: October 21, 2012

HIER_FSMS_DATAPATH.vhd

Project: TP2

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Mult <= Mult1*Mult2; if rising_edge(Clock) then if (En_AB = '1') then AB if (En_AC = '1') then AC if (En_AD = '1') then AD if (En_BC = '1') then BC if (En_BD = '1') then BD if (En_CD = '1') then CD end if; end process STAGE2;

<= <= <= <= <= <=

Mult; Mult; Mult; Mult; Mult; Mult;

end end end end end end

if; if; if; if; if; if;

--------------------------------------------- Generate sum values (Not FSM controlled) -------------------------------------------Sum1 <= AB + AC; Sum2 <= AD + BC; Sum3 <= BD + CD; NoSum <= BC; ----------------------------------------- Datapath stage 3 controlled by FSM3 ---------------------------------------STAGE3 : process(Sum1, Sum2, Sum3, NoSum, Mux3_Sel) begin case (Mux3_Sel) is when 0 => SerialOut <= Sum1; when 1 => SerialOut <= Sum2; when 2 => SerialOut <= Sum3; when 3 => SerialOut <= NoSum; when others => SerialOut <= Sum1; end case; end process STAGE3; end architecture RTL;

Page 2 of 2

Revision: TP2

Date: October 21, 2012

TP3_TCONTROL.VHD

Project: TP3_TRAIN

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-- FSM to control the trains library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity Tcontrol is port(reset, clock, sensor1, sensor2 sensor3, sensor4, sensor5 switch1, switch2, switch3 dirA, dirB (1 downto 0)); end Tcontrol;

: : : :

in std_logic; in std_logic; out std_logic; out std_logic_vector

architecture behavior of Tcontrol is type state_type is (ABout, Ain, Bin, Astop, Bstop); signal current_state, next_state : state_type; signal sensor12, sensor13, sensor24 : std_logic_vector(1 downto 0); begin State_Register : process(clock, reset) begin if reset = '1' then current_state <= ABout; elsif clock'event and clock = '1' then current_state <= next_state; end if; end process; LC1 : process (current_state, sensor1, sensor2, sensor3, sensor4, sensor5) begin next_state <= current_state; -- case statement to determine next state case current_state is when ABout => case sensor12 is when "00" => next_state <= ABout; when "01" => next_state <= Bin; when "10" => next_state <= Ain; when "11" => next_state <= Ain; when others => next_state <= ABout; end case; when Ain => case sensor24 is when "00" => next_state <= Ain; when "01" => next_state <= ABout;
Page 1 of 3 Revision: TP3_TRAIN

Date: October 21, 2012

TP3_TCONTROL.VHD

Project: TP3_TRAIN

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when "10" => next_state <= Bstop; when "11" => next_state <= ABout; when others => next_state <= ABout; end case; when Bin => case sensor13 is when "00" => next_state <= Bin; when "01" => next_state <= ABout; when "10" => next_state <= Astop; when "11" => next_state <= ABout; when others => next_state <= ABout; end case; when Astop => if sensor3 = '1' then next_state <= Ain; else next_state <= Astop; end if; when Bstop => if sensor4 = '1' then next_state <= Bin; else next_state <= Bstop; end if; end case; end process; -- LC2 -- combine bits for case statements above -- "&" operator combines bits sensor12 <= sensor1 & sensor2; sensor13 <= sensor1 & sensor3; sensor24 <= sensor2 & sensor4;

-- these outputs do not depend on the state switch3 <= '0'; -- outputs that depend on state with current_state select switch1 <= '0' when ABout, '0' when Ain, '1' when Bin, '1' when Astop, '0' when Bstop; with current_state select switch2 <= '0' when ABout, '0' when Ain, '1' when Bin,
Page 2 of 3 Revision: TP3_TRAIN

Date: October 21, 2012

TP3_TCONTROL.VHD

Project: TP3_TRAIN

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'1' when Astop, '0' when Bstop; with current_state select dirA <= "01" when "01" when "01" when "00" when "01" when with current_state select dirB <= "01" when "01" when "01" when "01" when "00" when end behavior;

ABout, Ain, Bin, Astop, Bstop;

ABout, Ain, Bin, Astop, Bstop;

Page 3 of 3

Revision: TP3_TRAIN

Date: October 21, 2012

TP3_TCONTROL.VHD

Project: TP3_TRAIN

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-- FSM to control the trains library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity Tcontrol is port(reset, clock, sensor1, sensor2 sensor3, sensor4, sensor5 switch1, switch2, switch3 dirA, dirB (1 downto 0)); end Tcontrol;

: : : :

in std_logic; in std_logic; out std_logic; out std_logic_vector

architecture behavior of Tcontrol is type state_type_A is (A_S41, A_S15, A_S51, A_S14, A_stop); type state_type_B is (B_S32, B_S24, B_S41, B_S13, B_stop_S2, B_stop_S4); signal pr_stA, nx_stA signal pr_stB, nx_stB : : state_type_A; state_type_B;

signal A_wait, B_wait, A_back : std_logic; begin State_Register_A_B : process(clock, reset) begin if reset = '1' then pr_stA <= A_S41; pr_stB <= B_S32; elsif clock'event and clock = '1' then pr_stA <= nx_stA; pr_stB <= nx_stB; end if; end process; LC1_LC2_A : process (pr_stA, sensor1, sensor2, sensor3, sensor4, sensor5) begin nx_stA <= pr_stA; switch3 <= '0'; A_wait <= '0'; A_back <= '0'; dirA <= "01"; -- case statement to determine next state case pr_stA is when A_S41 => A_back <= '1';
Page 1 of 3 Revision: TP3_TRAIN

Date: October 21, 2012

TP3_TCONTROL.VHD

Project: TP3_TRAIN

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if sensor1 = '1' then nx_stA <= A_S15; end if; when A_S15 => A_back <= '1'; dirA <= "10"; switch3 <= '1'; if sensor5 = '1' then nx_stA <= A_stop; end if; when A_S51 => switch3 <= '1'; if sensor1 = '1' then nx_stA <= A_S14; end if; when A_S14 => dirA <= "10"; if sensor4 = '1' then nx_stA <= A_S41; end if; when A_stop => dirA <= "00"; A_wait <= '1'; if B_wait = '0' and sensor1 = '0' then nx_stA <= A_S51; end if; end case; end process LC1_LC2_A; LC1_LC2_B : process (pr_stB, sensor1, sensor2, sensor3, sensor4, sensor5) begin nx_stB <= pr_stB; switch1 <= '0'; switch2 <= '0'; B_wait <= '0'; dirB <= "01"; -- case statement to determine next state case pr_stB is when B_S32 => if sensor2 = '1' then nx_stB <= B_stop_S2; end if; when B_S24 => switch1 <= '1'; B_wait <= '1'; if sensor4 = '1' then nx_stB <= B_stop_S4;
Page 2 of 3 Revision: TP3_TRAIN

Date: October 21, 2012

TP3_TCONTROL.VHD

Project: TP3_TRAIN

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end if; when B_S41 => B_wait <= '1'; if sensor1 = '1' then nx_stB <= B_S13; end if; when B_S13 => switch2 <= '1'; if sensor3 = '1' then nx_stB <= B_S32; end if; when B_stop_S2 => dirB <= "00"; B_wait <= '1'; if A_back = '1' and sensor4 = '0' then nx_stB <= B_S24; end if; when B_stop_S4 => dirB <= "00"; B_wait <= '1'; if A_wait = '1' then nx_stB <= B_S41; end if; end case; end process LC1_LC2_B; end behavior;

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Revision: TP3_TRAIN