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Implementation of Convolution

This paper presents an efficient FPGA implementation of convolution that can perform convolution on an acquired image in real time. The proposed implementation uses a modified hierarchical design approach to significantly reduce computation time, power consumption, hardware resources, and area. It provides modularity, expandability, and regularity to form different convolutions for any number of bits. Convolution has many applications in image processing and discrete signal processing.

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Pradeepdarshan Pradeep
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39 views

Implementation of Convolution

This paper presents an efficient FPGA implementation of convolution that can perform convolution on an acquired image in real time. The proposed implementation uses a modified hierarchical design approach to significantly reduce computation time, power consumption, hardware resources, and area. It provides modularity, expandability, and regularity to form different convolutions for any number of bits. Convolution has many applications in image processing and discrete signal processing.

Uploaded by

Pradeepdarshan Pradeep
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Efficient FPGA implementation of convolution

ABSTRACT

Many image processing operations such as scaling and rotation require re-sampling or convolution filtering for each pixel in the image. Convolutions on digital images are important since they represent operations that are more general than the operations that can be performed on analog images. Convolution has many applications which have great significance in discrete signal processing. It is usually difficult to deal with analog signals. Hence signals are converted to digital state. Filtering of signals is very important in order to determine which one to accept and which one to reject, and all of that is done by convolution. This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized by simplifying the convolution building blocks. The purpose of this research is to prove the feasibility of an FPGA that performs a convolution on an acquired image in real time. The proposed implementation uses a modified hierarchical design approach, which efficiently and accurately speeds up computation; reduces power, hardware resources, and area significantly. The efficiency of the proposed convolution circuit is tested by embedding it in a top level FPGA. In addition, the presented circuit uses less power consumption and delay from input to output. It also provides the necessary modularity, expandability, and regularity to form different convolutions for any number of bits.
Head office: 2nd floor, Solitaire plaza, beside Image Hospital, Ameerpet, Hyderabad
www.kresttechnology.com, E-Mail : [email protected] , Ph: 9885112363 / 040 44433434

APPLICATION: Image Compression Applications ADVANTAGES: Power reduction Reduction of Hardware complexity LANGUAGE USED: Verilog HDL TOOLS REQUIRED: MODELSIM Simulation XILINX-ISE Synthesis

Head office: 2nd floor, Solitaire plaza, beside Image Hospital, Ameerpet, Hyderabad
www.kresttechnology.com, E-Mail : [email protected] , Ph: 9885112363 / 040 44433434

Head office: 2nd floor, Solitaire plaza, beside Image Hospital, Ameerpet, Hyderabad
www.kresttechnology.com, E-Mail : [email protected] , Ph: 9885112363 / 040 44433434

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