Processor Design 5Z032: Interfacing Processors and Peripherals
Processor Design 5Z032: Interfacing Processors and Peripherals
Topics
Examples
Buses
Introduction
I/O Design affected by many factors (expandability, cost, performance, standards, availability)
Performance:
access latency throughput connection between devices and the system the memory hierarchy the operating system
Cache
Main memory
I/O controller
I/O controller
I/O controller
Disk
Processor Design 5Z032
Disk
Graphics output
Network
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I/O
I/O example
What will happen in 5 years if CPUs get faster 50% each year but I/O performance stays constant Answer:
CPU time reduces to 22 seconds I/O time increases from 10% to 45% !!!
I/O Devices
To access data:
seek: position head over the proper track (8 to 20 ms. avg.) rotational latency: wait for desired sector (.5 / RPM) transfer: grab the data (one or more sectors) 2 to 15 MB/sec
Platters
Tracks
Platter Sectors
Track
Types of buses:
processor-memory (short high speed, custom design) backplane (high speed, often standardized, e.g., PCI) I/O (lengthy, different devices, standardized, e.g., SCSI)
Look at some examples from the text Performance Analysis of Synchronous vs. Asynchronous Performance Analysis of Two Bus Schemes
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Bus Arbitration:
daisy chain arbitration (not very fair) centralized arbitration (requires an arbiter), e.g., PCI self selection, e.g., NuBus used in Macintosh collision detection, e.g., Ethernet
Operating system:
polling interrupts DMA
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