Design of A USB Device Driver (Overview) .
Design of A USB Device Driver (Overview) .
Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
USB Overview
? Hardware Overview
Topology
? Protocol Characteristics
Packet Types USB Transactions
? Enumeration
Enumeration States
Hardware Overview
HUB HUB HOST/HUB
?Topology
Kbd
Monitor
PC
Pen
Mouse
Speaker
Mic
Phone
Tiered Star (Distributes Connectivity Points) 127 logical connections (up to 5 meters per segment) Up to 6 tiers
?Bus transactions
Speed: 12Mbps aggregate Isochronous and Asynchronous Media access controlled by host
1.5Mbps sub-channel
?Configuration
Phone
Dynamic insertion-removal Autoconfiguration on change 2-wire differential signaling, NRZI coded with bit stuffing 4 pin connector, 4 wire cable Supply Sourcing +5V
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?Physical Layer
Data from host-to-function and function-to-host Host handles most of the protocol complexity Peripheral design is simple and low-cost
? Robustness
Handshake to acknowledge data transfer and flow control Very low raw physical bit error rate ( <10 -10 ) CRC protection plus hardware retry option Data Toggle Sequence bits Data transfer bandwidth and latency prenegotiated Flow control for peripheral buffer management
Token Data Transfer
Handshake
Packet Types
? Token - OUT, IN, SOF, SETUP
First packet in any transaction Specifies function address, endpoint Specifies data direction 0 - 1023 bytes
? Special - PRE
Token
IN
OUT
SET
T/O
NAK
STALL Idle
DATA0 T/O
Handshake ACK
ACK
NAK
STALL
T/O
ACK Idle
Host
Function
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Device
Buffers
No USB Format
Interface Specific
Endpoint Zero
a collection of endpoints
Unspecified
USB Bus Interface
Transactions
Pipe, connection abstraction between two horizontal layers Data transport mechanism
USB-relevant format of transported data 9
Idle Bus
Configured
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Hub
Connect Cable
Device
Attached
Configured
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Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
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? Combination USB Host and USB Peripheral chip ? Combination micro-processor and USB Core
8/16 bit processor Mitsubishi, .etc
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Input and Output FIFOs for Control Endpoint Input or Output FIFO for other Endpoints
Register Bank USB Internal Bus EPx Status Reg EPx Ctl Reg EP 0 Control EP 1 Bulk/ISO IN EP2 Bulk/Iso Out EP3 Interrupt IN USB Control Reg
USB Pads
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Setup, Suspend, Resume, SOF, Reset, Zero Byte Packet DMA Complete Transmit/Receive Ack/Nack/Error status Ack/ Nack/Error FIFO empty/full or at high/low threshold level multiple packet depth Hardware Retry of Packet Transfers on error
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? FIFOs supporting
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Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
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Application
API
Driver
Logical pipe Logical pipe
Fifo
Fifo
Hardware
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System Architecture
ISR Thread USB Protocol Thread Main Thread USB Controller Hardware File System Thread
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Control, Bulk, Isochrnous, Interrupt Endpoints Isochrnous, Attach/Dettach, SOF, Suspend/Resume Attach/Dettach,
? Main Thread
Thread which executes the product application Calls and is triggered by Callback from USB Driver layer Lower Priority File System Thread
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Interrupt Sources
? SOF ? Attach/Dettach Attach/Dettach ? Suspend/Resume ? Setup Packet ? Data IN Ack ? Data OUT Ack ? FIFO Empty or Low level threshold met ? FIFO Full or High level threshold met ? DMA Complete
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USB Driver
EP0 Fifo s
EP1 Fifo
EP2 Fifo
EP3 Fifo
To Host
Hardware
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Enumeration
USB Driver
EP0 Fifo s
EP1 Fifo
EP2 Fifo
EP3 Fifo
To Host
Hardware
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Application
(Main Thread)
IN OUT IN Logical pipes
USB Driver
EP0 Fifo s
EP1 Fifo
EP2 Fifo
EP3 Fifo
To Host
Hardware
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Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
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Power
Management
Attach/ Detach
Control Protocol
- Standard Requests - Bulk In/Out - Class Requests - Isochronous In/Out - Vendor Requests - Interrupt In/Out
USB Driver Low Level Access Methods and ISRs Pull-Up Resistor USB Controller Registers Endpoint FIFO Registers
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Utilities
UsbOpen
UsbClose
UsbRead
UsbWrite
UsbIoctl
UsbIsr
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Disables DMA controller use of endpoint FIFO s s Set endpoint state to CLOSED
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USBRead() USBRead()
? Read from Bulk, Isochronous or Interrupt endpoint
Verify endpoint is open If transfer mode is DMA else ISR Called
Setup and start DMA read of fixed size from Endpoint FIFO Block until DMA is complete or a timeout occurs
Loop until all data is read, a timeout occurs or a short packet is received Exit ISR
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USB Host
Data Buffer
ACK Data Packet Out Token Data Packet Data Packet ACK
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USBWrite() USBWrite()
? Write to Bulk, Isochronous or Interrupt endpoint
Verify endpoint is open If transfer mode is DMA else
Setup and start DMA write of fixed size to Endpoint FIFO Block until DMA is complete or a timeout occurs ISR Called Loop until all data is written, or a timeout occurs Exit ISR
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Endpoint FIFO
USB Host
Data Buffer
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Control Read
? Call USBRead( EP0 ) to read a Setup Packet USBRead(
Read from EP0 OUT FIFO
Standard, Class or Vendor For example prepare to return a Descriptor Perform normal USBWrite() function to EP0 IN FIFO USBWrite() Wait for Host to return a Zero Byte packet terminating Control transfer
? Repeat
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Control Write
? Call USBRead( EP0) to read a Setup Packet USBRead(
Read from EP0 OUT FIFO
? Prepare to receive data from Host ? Call USBRead( EP0 ) to read data from the Host USBRead(
Perform normal USBRead() function from EP0 OUT USBRead() FIFO Send a Zero Byte packet to the Host terminating the Control transfer
? Repeat
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Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
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Windows 98 OS
Application
User-mode minidriver
User Mode
WDM still image driver for USB
Driver Interface
Kernel Mode
USB
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WDM Still Image Architecture Attempts to Keep All Custom Software in User Mode
Application
Still Image Still Image Control Control Panel Panel Still Image Still Image Event Event Monitor Monitor Still Image Still Image Control Control Center Center
TWAIN API
ISIS API
WDM Still Image WDM Still Image MiniDriver for USB MiniDriver for USB USB USB
WDM Still Image WDM Still Image MiniDriver for SCSI MiniDriver for SCSI SCSI SCSI
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Design Constraints
? Hardware Selection
Still image architecture requires Control, Bulk In, Bulk Out and Interrupt endpoints.
Design of the communications protocol is contingent on the Twain data source and any classes supported. Features supported by camera application Power Management requirements
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Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
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Use analyzer for documenting test results Debug Driver enumeration and Data Transfer Verify System level behavior with analyzer Execute Compliance Test in loop mode (>1000x)
? Purchase a USB Evaluation Board & source code ? Utilize USB Organizations Test Resources
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Analyzer View
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? System Tests
Open/Close endpoints Data Transfer (read and write) Select Endpoint using DMA Control Test IO
? System Tests
Perform typical use cases with Product software System Level Power Management
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Compliance Workshops
Verifies USB Compliance and Interoperability in-house USB Compliance and Interoperability
Verify throughout product development
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USB Analyzers
? Benefits of an USB Analyzer Tool
Passively monitors USB Bus Allows debug of Enumeration, Vendor/Class Requests Reveals system level behavior Some tools allow for active introduction of faults, standard Requests or Vendor/Class Requests
? Drawbacks
Purchase Price Selecting which one you want Some PC have demonstrated signal/noise errors s with USB analyzer attached s
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Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
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Issues to consider
? More Class Support
HID, Common, Mass Storage, Firmware Upgrade,
? USB 2.0
? Protocol Stacks
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Outline
? USB Overview ? USB Hardware Controllers ? Architecture of an Embedded USB Device ? USB Device Driver Architecture ? Case Study of a USB Device Driver ? Testing Strategies ? Issues to consider ? Conclusions
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Conclusion
? Selecting a more capable USB controller simplifies the design USB Device Drivers ? Support both CPU and DMA transfers ? Data Transfer Speed is a priority
Transfer Data inside ISR Optimize code execution of critical routines Design a solution with parallelism of processing and data transfer Dedicate the DMA to the highest bus bandwidth scenarios
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? USB System Architecture, Don Anderson Mindshare Inc. ? www.linux.org www.linux.org ? www.catc.com www.catc.com ? Questra Corporation (716) 381-0260 www.questra.com www.questra.com
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