SYNAPSE Techno Design Innovation Pvt Ltd

Advanced eXtensible Interface(AXI)

By : Prithvinarayan(EMP ID:225) K.T Santosh (EMP ID:216) R.Sushma (EMP ID:237)

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Agenda
Introduction Where AXI reside? Signals and Channels Read Burst Operation

Write Burst Operation

Transaction Structure

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Introduction
targeted at high-performance, high-frequency system designs

AXI bus interface provides high bandwidth between the processor, on-chip RAM, peripherals, and interfaces to external memory.
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Introduction
Variable-length bursts

Contd

From 1 to 16(AXI3) data transfers (called beats) per burst From 1 to 256(AXI4)

Bursts with a transfer size of 8-1024 bits Wrapping, incrementing, and fixed. Locked accesses

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Where does AXI Reside?

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Interconnect, Interface & Channel

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Channels
Write Address/Control

Contd
AWREADY

Write data
WREADY

AXI Master

Write Response
BREADY

AXI Slave

Read Address/Control
ARREADY

Read data
RREADY
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Write Channel
SIGNALS -SOU RCE AWID[3:0] ------- M AWADDR[31:0]- M AWLEN[7:0] AWSIZE[2:0] AWBURST[1:0] AWVALID -----AWREADY M M M M S

Prefix - AW

Prefix - B
BID[3:0] -----S

BRESP[1:0] -----BVALID BREADY

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S
S M

Read Channel
Prefix - AR

Prefix - R

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Write Operation
Note: data transfers only when valid = ready = 1

Write request A is accepted

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Response completes write operation

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Read Operation
Note: data transfers only when valid = ready = 1

Read request is initiated

Data read is ready

1st data is transferred

Read request is accepted

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The last data is transferred

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Overlapping Read Burst

Read request A is accepted Read request B is accepted via AR channel while data A(0) is transferred via R channel
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Transaction Structure
Burst Addressing
ADDRESS A11 A21 A31

DATA

D11

D12 D13 D14 D21

D22 D23 D31

A21

MASTER ID MASTER 1 TRANSACTION ID 2nd TRANSACTION

Separation of address and data channel

Master provides the start address of burst Slave needs to generate the remaining addresses based on burst type (FIXED, INCR, WRAP)
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Address structure

Burst Length no. of data transfers that can occur within each burst AWLEN/ARLEN[7:0] The burst length for AXI3 is defined as, Burst_Length = AxLEN[3:0] + 1 The burst length for AXI4 is defined as, Burst_Length = AxLEN[7:0] + 1,

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Burst Size
ARSIZE/AWSIZE[3:0] Max no. of data bytes to transfer in each beat within a burst

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Burst Type
ARBURST/AWBURST[1:0]: 3 types of bursts
Fixed Incrementing Wrapping

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Locked Access
Normal access, AR(W)LOCK[1:0]=b00 Exclusive access, b01
Exclusive read Exclusive write If no intervening write to the address region, EXOKAY response. If not, OKAY response.

Locked access, b11

Start with b11, and end with b00 During the period, only the lock initiating master can access the address region (not the slave!!!)
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Out-of-Order Addressing
ADDRESS A11 A21 A31

RDATA

D21 D22 D23

D31

D11 D12 D13 D14

Transaction ID is used to identify data transfer at all channels

ARID, AWID, RID, WID, & BID

Ordering by transaction ID
Master needs to finish data transfers with the same transaction ID in the order of request issue. Slave can handle data transfers with different transaction IDs out-of-order
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Aligned & Unaligned Transfers

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AHB vs. AXI Burst

AHB Burst
Address and Data are locked together (single pipeline stage) HREADY controls intervals of address and data

AXI Burst
One Address for entire burst

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AXI Out of Order Completion

With AHB
If one slave is very slow, all data is held up

With AXI Burst

Multiple outstanding addresses, out of order (OO) completion allowed Fast slaves may return data ahead of slow slaves

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AXI Burst

AXI Burst
Simultaneous read, write transactions Better bus utilization

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FOR MORE INFORMATIONS , REFER TO THE SPECs PROVIDED BY ARM. THEY ARE ALSO ATTACHED HERE IHI0022D_amba_axi_protocol_spec amba_axi4

THANK YOU

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SUPPORTING SLIDES

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AWID[3:0] AWADDR[31:0] AWLEN[7:0] AWSIZE[3:0] AWBURST[1:0] AWLOCK[1:0] AWCACHE[3:0] AWQOS AWREGION AWPROT[2:0] AWVALID AWREADY (S)

WID WDATA WSTRB WREADY WVALID WUSER WLAST BID BRESP BUSER BVALID BREADY

ARID[3:0] ARADDR[31:0] ARLEN[3:0] ARSIZE[3:0] ARBURST[1:0] ARLOCK[1:0] ARCACHE[3:0] ARQOS ARREGION ARPROT[2:0] ARVALID ARREADY (S)

RID RDATA RREADY RVALID RUSER RLAST RRESP

BACK

BACK

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Write Interleaving
Interleaving rule
Data with different ID can be interleaved. The order within a single burst is maintained The order of first data needs to be the same with that of request Write Interleave Cability The maximum number of transactions that master can interleave
ADDRESS A11 A21 A31

DATA

D11 D21 D22 D12 D23 D31 D13

D14

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