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EE115C Digital Electronic Circuits: Pass Transistor Logic

The document discusses pass transistor logic (PTL) used in digital circuits. It describes some issues with PTL, such as improper switching and delay, and presents several solutions. Specifically, it introduces level restoring transistors to address improper switching by restoring the output voltage swing. It also discusses using zero threshold voltage transistors or transmission gates as alternatives. The document notes transmission gates require more control signals but allow bidirectional switching. Finally, it warns that cascading many PTL gates can lead to excessive delay.

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trwilson1304
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
55 views

EE115C Digital Electronic Circuits: Pass Transistor Logic

The document discusses pass transistor logic (PTL) used in digital circuits. It describes some issues with PTL, such as improper switching and delay, and presents several solutions. Specifically, it introduces level restoring transistors to address improper switching by restoring the output voltage swing. It also discusses using zero threshold voltage transistors or transmission gates as alternatives. The document notes transmission gates require more control signals but allow bidirectional switching. Finally, it warns that cascading many PTL gates can lead to excessive delay.

Uploaded by

trwilson1304
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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EE115C Digital Electronic Circuits

Lecture 11a:

Pass Transistor Logic

Example: AND Gate


B
A 0 0 1 1 B 0 1 0 1 F 0 0 0 1

A B F = AB 0

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General Pass Transistor Logic (PTL)


B

Inputs

Switch Network

Out

Out
B B

Allows primary inputs to drive S and D terminals !

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PTL Problem #1 : Improper Switch


C = 2.5V A = 2.5 V B CL A = 2.5 V Mn M1 C = 2.5 V M2 B

VB does not pull up to 2.5V, but to 2.5V VTn

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PTL Problem #1 : Improper Switch (contd.)

3.0

In In

Voltage [V]

1.5 m/0.25 m VDD x Out 0.5 m/0.25 m 0.5 m/0.25 m

2.0

Out x

1.0

0.0

0.5

1.5

Time [ns]

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Solution 1: Level Restoring Transistor


VDD

Level Restorer
B A Mn Mr X

VDD

M2 Out M1

Advantage: Full swing Restorer adds capacitance, takes away PDN current at X Ratio problem
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Restorer Sizing
Voltage at node x [V]
3.0

W/Ln = 0.5m / 0.25m


W /Lr =1.75/0.25 W /L r =1.50/0.25

2.0

1.0 W/ Lr =1.0/0.25 0.0 0 100 200 300 400 500 W /L r =1.25/0.25

Time [ps]

Upper limit on restorer size Pass-transistor PDN can have several transistors in stack
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Solution 2: Zero VT Transistors


VDD A 0V

Zero VT transistors
VDD 2.5V

VDD A 2.5V

0V

Out

Watch out for leakage currents


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Solution 3: Transmission Gate


C A C B A C C B

Requires two transistors More control signals needed

C = 2.5 V A = 2.5 V B CL C=0V

Bidirectional switch Rail-to-rail switching

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Resistance of Transmission Gate


30

off sat
Resistance, ohms
20 Rp 2.5 V Vou t Rp 10 Rn 2.5 V Rn

sat
Rn || Rp

lin

0V

Vout: 0 1
0 0.0 1.0 Vou t , V 2.0

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10

Pass Transistor based Multiplexer

S A S

VDD

M2 F M1

F = A S + B S

B S

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11

Transmission Gate XOR


B
B M2 A M1 B A F M3/M4

6 transistors only 12 transistors in CMOS

B on for B=1
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on for B=0
12

PTL Problems #2 : Delay


2.5 V1 In 0 Vi-1 C 0 (a) Req In Req Vi C C Req Vi+1 C Req Vn C 2.5 Vi C 2.5 Vi+1 0 C Vn-1 C 2.5 Vn 0 C

V1

Vn-1 C

(b) m Req In C CC C C CC C Req Req Req Req Req

(c)

Too much delay if many gates are used in series !


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