CY7C1041DV33

4-Mbit (256 K 16) Static RAM

4-Mbit (256 K 16) Static RAM

Features

Functional Description
The CY7C1041DV33 is a high performance CMOS Static RAM organized as 256 K words by 16-bits. To write to the device, take chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 to I/O7) is written into the location specified on the address pins (A0 to A17). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 to I/O15) is written into the location specified on the address pins (A0 to A17). To read from the device, take chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If BHE is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. The input and output pins (I/O0 to I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C1041DV33 is available in a standard 44-pin 400-mil wide SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout and a 48-ball FBGA package.

Temperature ranges Industrial: 40 C to 85 C Pin and function compatible with CY7C1041CV33 High speed tAA = 10 ns Low active power ICC = 90 mA Low CMOS standby power ISB2 = 10 mA 2.0 V data retention Automatic power-down when deselected TTL compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded SOJ, and 44-pin TSOP II Packages

Logic Block Diagram

INPUT BUFFER

A0 A1 A2 A3 A4 A5 A6 A7 A8

ROW DECODER

SENSE AMPS

IO0IO7 IO8IO15

256K 16

COLUMN DECODER

A9 A10 A 11 A 12 A 13 A14 A15 A16 A17

BHE WE CE OE BLE

Cypress Semiconductor Corporation Document Number: 38-05473 Rev. *K

198 Champion Court

San Jose, CA 95134-1709

408-943-2600 Revised June 1, 2011

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Contents
Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 AC Switching Characteristics ......................................... 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18

Document Number: 38-05473 Rev. *K

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Selection Guide
Description Maximum access time Maximum operating current Maximum CMOS standby current -10 (Industrial) 10 90 10 Unit ns mA mA

Pin Configuration
Figure 1. 48-ball VFBGA (Pinout 1) [1, 2]
1 BLE IO 0 IO 1 VSS VCC IO 6 IO 7 NC 2 OE BHE IO2 IO3 IO4 IO 5 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE IO10 6 NC IO 8 IO 9 A B C D E F G H

Figure 2. 48-ball VFBGA (Pinout 2) [1, 2]

1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 NC 2 OE BHE IO10 IO 11 IO 12 IO 13 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE IO 1 IO3 IO 4 IO 5 WE A11 6 NC IO 0 IO 2 VCC VSS IO 6 IO 7 NC A B C D E F G H

IO11 VCC IO12 IO13 WE A11 VSS IO14 IO15 NC

Figure 3. 44-pin SOJ/TSOP II

A0 A1 A2 A3 A4 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A14 A13 A12 A11 A10

Notes 1. NC pins are not connected on the die. 2. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8] balls) are swapped.

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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ 65 C to +150 C Ambient temperature with power applied .......................................... 55 C to +125 C Supply voltage on VCC relative to GND [3] ...0.3 V to +4.6 V DC voltage applied to outputs in high Z State[3] .................................. 0.3 V to VCC +0.3 V DC input voltage[3] .............................. 0.3 V to VCC + 0.3 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage .......................................... > 2001 V (MIL-STD-883, method 3015) Latch-up current .................................................... > 200 mA

Operating Range
Range Industrial Ambient Temperature 40 C to +85 C VCC 3.3 V 0.3 V Speed 10 ns

DC Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH IIX IOZ ICC
[3]

Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current

Test Conditions VCC = Min, IOH = 4.0 mA VCC = Min, IOL = 8.0 mA

-10 (Industrial) Min 2.4 2.0 0.3 Max 0.4 VCC + 0.3 0.8 +1 +1 90 80 70 60 20 10

Unit V V V V A A mA mA mA mA mA mA

VIL[3]

GND < VI < VCC GND < VOUT < VCC, output disabled VCC = Max, f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz

1 1

ISB1 ISB2

Automatic CE power-down current TTL Max VCC, CE > VIH, inputs VIN > VIH or VIN < VIL, f = fMAX Automatic CE power-down current CMOS inputs Max VCC, CE > VCC 0.3 V, VIN > VCC 0.3 V, or VIN < 0.3 V, f = 0

Note 3. Minimum voltage is 2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.

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Capacitance
Parameter[4] CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 8 8 Unit pF pF

Thermal Resistance
Parameter[4] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still Air, soldered on a 3 4.5 inch, four layer printed circuit board 48-ball FBGA Package 27.89 14.74 44-pin SOJ Package 57.91 36.73 44-pin TSOP II Unit Package 50.66 17.17 C/W C/W

AC Test Loads and Waveforms

The AC test loads and waveform diagram follows.[5]

10 ns device
OUTPUT

Z = 50 50 30 pF*

3.0 V GND

ALL INPUT PULSES 90% 10% 90% 10%

* CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT High Z Characteristics 3.3 V OUTPUT 5 pF R 317

1.5 V Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns

R2 351 (c)

Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except high Z) are tested using the load conditions shown in AC Test Loads and Waveforms (a). High Z characteristics are tested for all speeds using the test load shown in AC Test Loads and Waveforms (c).

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AC Switching Characteristics
Over the Operating Range[6] Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(Typical) to the first access Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z[8] Z[8, 9] Z[8, 9] OE HIGH to high CE HIGH to high 100 10 3 0 3 0 0 10 7 7 0 0 7 5 0 3 7 10 10 5 5 5 10 5 6 5 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description 10 (Industrial) Min Max Unit

CE LOW to low Z[8] CE LOW to power-up CE HIGH to power-down Byte enable to data valid Byte enable to low Z Byte disable to high Z
[10, 11]

Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE HIGH to low Z[8] WE LOW to high Z[8, 9] Byte enable to end of write

Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads and Waveforms. Transition is measured when the outputs enter a high impedance state. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR[13] tR
[14]

Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time

Conditions[12] VCC = VDR = 2.0 V, CE > VCC 0.3 V, VIN > VCC 0.3 V or VIN < 0.3 V

Min 2.0 0 tRC

Max 10

Unit V mA ns ns

Data Retention Waveform

DATA RETENTION MODE VCC CE 3.0 V tCDR VDR > 2 V 3.0 V tR

Switching Waveforms
Figure 4. Read Cycle No. 1[15, 16]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID

Notes 12. No input may exceed VCC + 0.3 V. 13. Tested initially and after any design or process changes that may affect these parameters. 14. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 15. Device is continuously selected. OE, CE, BHE, and BLE = VIL. 16. WE is HIGH for read cycle.

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Switching Waveforms (continued)
Figure 5. Read Cycle No. 2 (OE Controlled)[17, 18]

ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE

HIGH IMPEDANCE

IICC CC IISB SB

Figure 6. Write Cycle No. 1 (CE Controlled)[19, 20]

tWC ADDRESS

CE

tSA

tSCE

tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD

tHA

Notes 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE transition LOW. 19. Data I/O is high impedance if OE or BHE and BLE = VIH. 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

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Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS

BHE, BLE

tSA

tBW

tAW tPWE WE tSCE CE tSD DATAI/O tHD

tHA

Figure 8. Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[21, 22]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA

OE

BHE, BLE t DATA I/O NOTE 23 t

HZOE SD

tHD

DATAIN VALID

Notes 21. Data I/O is high impedance if OE or BHE and BLE = VIH. 22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 23. During this period the I/Os are in the output state and input signals should not be applied.

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Switching Waveforms (continued)
Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW)
tWC ADDRESS

CE

tSCE

tAW tSA WE tBW BHE, BLE tHZWE DATA I/O NOTE 24 tSD tHD tPWE

tHA

tLZWE

Truth Table
CE H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L L H L L H X H BHE X L H L L H L X H I/O0I/O7 High Z Data out Data out High Z Data in Data in High Z High Z High Z I/O8I/O15 High Z Data out High Z Data out Data in High Z Data in High Z High Z Power-down Read all bits Read lower bits only Read upper bits only Write all bits Write lower bits only Write upper bits only Selected, outputs disabled Selected, outputs disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)

Note 24. During this period the I/Os are in the output state and input signals should not be applied.

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Ordering Information
Speed (ns) 10 Ordering Code CY7C1041DV33-10BVI CY7C1041DV33-10BVXI CY7C1041DV33-10BVJXI CY7C1041DV33-10VXI CY7C1041DV33-10ZSXI Package Diagram Package Type 48-ball VFBGA (Pb-free) Pinout - 1[25] 48-ball VFBGA (Pb-free) Pinout - 2[25] 51-85082 44-pin (400-mil) Molded SOJ (Pb-free) 51-85087 44-pin TSOP II (Pb-free) Operating Range Industrial 51-85150 48-ball VFBGA Pinout - 1[25]

Please contact your local Cypress sales representative for availability of these parts

Ordering Code Definitions

CY 7 C 1 04 1 D V33 - 10 XXX X I Temperature Range: I = Industrial Pb-free Package Type: xxx = BV or BVJ or V or ZS BV = 48-ball VFBGA Pinout - 1 BVJ = 48-ball VFBGA Pinout - 2 V = 44-pin (400-mil) Molded SOJ ZS = 44-pin TSOP II Speed: 10 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 1 = Data width 16-bits 04 = 4-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress

Note 25. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8] balls) are swapped.

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Package Diagrams
Figure 1. 48-ball VFBGA (6 8 1 mm) BV48/BZ48, 51-85150
a

51-85150 *F

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Package Diagrams (continued)
Figure 2. 44-pin Molded SOJ (400-mil) V44.4, 51-85082

51-85082 *C

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Package Diagrams (continued)
Figure 3. 44-pin TSOP Z44-II, 51-85087

51-85087 *C

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Acronyms
Acronym CE CMOS FBGA I/O OE SOJ SRAM TSOP TTL VFBGA WE chip enable complementary metal oxide semiconductor fine-pitch ball grid array Input/output output enable small outline J-lead static random access memory thin small outline package transistor-transistor logic very fine-pitch ball grid array write enable Description

Document Conventions
Units of Measure
Symbol C MHz A s mA mm ns % pF V W degree Celcius Mega Hertz micro Amperes micro seconds milli Amperes milli meter nano seconds percent pico Farad Volts Watts Unit of Measure

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Document History Page

Document Title: CY7C1041DV33, 4-Mbit (256 K 16) Static RAM Document Number: 38-05473 Rev. ** *A *B ECN No. 201560 233729 351117 Orig. of Change SWI RKF PCI Submission Date See ECN See ECN See ECN Description of Change Advance Data sheet for C9 IPP 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the Ordering information Changed from Advance to Preliminary Removed 15 and 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Coml and Indl temperature ranges ICC (Coml): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10 and 12ns speed bins respectively ICC (Indl): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in Note# 2 Changed Note# 4 on AC Test Loads Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Added Data Retention Characteristics/Waveform and footnote # 11, 12 Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed Package Diagram name from 44-Pin TSOP II Z44 to 44-Pin TSOP II ZS44 and from 44-Pin (400-mil) Molded SOJ V34 to 44-Pin (400-mil) Molded SOJ V44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns Product Information Added Pin-Free Ordering Information Shaded Ordering Information Table Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Included Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High-Z parameter measurement Updated the ordering information and replaced Package Name column with Package Diagram in the Ordering Information Table Added -10BVI product ordering code in the Ordering Information table Added -10BVJXI part Added Automotive-A information For 12 ns speed, changed ISB1 spec from 25 mA to 15 mA For 12 ns speed, changed tDOE and tDBE specs from 6 ns to 7 ns Updated ordering information table Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits Corrected typo in Note 20. No technical updates. No technical updates

*C

446328

NXR

See ECN

*D *E *F

480177 2541850 2752971

VKN VKN/PYRS VKN

See ECN 07/22/08 08/18/2009

*G

3034079

PRAS

09/20/2010

*H *I *J

3082285 3149096 3182129

HRP AJU HRP

11/09/2010 01/24/2011 03/02/2011

Document Number: 38-05473 Rev. *K

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Document History Page (continued)
Document Title: CY7C1041DV33, 4-Mbit (256 K 16) Static RAM Document Number: 38-05473 Rev. *K ECN No. 3271586 Orig. of Change PRAS Submission Date 06/01/2011 Description of Change Updated Features (Dislodged automotive part information to 001-69789). Updated Functional Description (Removed For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.). Updated Selection Guide (Dislodged automotive part information to 001-69789). Updated Operating Range (Dislodged automotive part information to 001-69789). Updated DC Electrical Characteristics (Dislodged automotive part information to 001-69789). Updated AC Switching Characteristics (Dislodged automotive part information to 001-69789). Updated Data Retention Characteristics (Dislodged automotive part information to 001-69789). Updated Truth Table. Updated Ordering Information (Dislodged automotive part information to 001-69789). Updated in new template.

Document Number: 38-05473 Rev. *K

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Sales, Solutions, and Legal Information
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Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-05473 Rev. *K

Revised June 1, 2011

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