Vlsi Lab Manual5
Vlsi Lab Manual5
AIM: Design of four bit Magnitude Comparator 1) Using Structural Method:VHDL Program:library ieee; use ieee.std_logic_1164.all; entity COM is port (A0,A1,A2,A3,B0,B1,B2,B3 : inout bit; E,G,L : out bit); end COM; architecture test of COM is begin process(A0,A1,A2,A3,B0,B1,B2,B3) variable T1,T2,T3,T0 : bit; begin T3 := A3 xnor B3; T2 := A2 xnor B2; T1 := A1 xnor B1; T0 := A0 xnor B0; E <= T3 and T2 and T1 and T0;
G <= (A3 and ( not B3)) or (T3 and A2 and ( not B2)) or (T3 and T2 and A1 and (not B1)) or (T3 and T2 and T1 and A0 and (not B0)); L <= (( not A3) and B3) or (T3 and (not A2) and B2) or (T3 and T2 and (not A1) and B1) or (T3 and T2 and T1 and (not A0)and B0); end process; end test;
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VECTOR WAVEFORM:-
VLSI TECHNOLOGY
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VHDL Program:library ieee; use ieee.std_logic_1164.all; entity COM is port (A0,A1,A2,A3,B0,B1,B2,B3 : in bit; E,G,L : out bit); end COM; architecture test of COM is begin E <= ( A3 xnor B3) and (A2 xnor B2) and (A1 xnor B1) and (A0 xnor B0);
B3) and (A2 xnor B2) and A1 and (not B1)) or ((A3 xnor B3) and (A2 xnor B2) and ( A1 xnor B1) and A0 and (not B0));
G <= (A3 and ( not B3)) or ((A3 xnor B3) and A2 and ( not B2)) or ((A3 xnor
L <=
(( not A3) and B3) or ((A3 xnor B3) and (not A2) and B2) or ((A3 xnor B3) and(A2 xnor B2) and (not A1) and B1) or ((A3 xnor B3) and (A2 xnor B2) and ( A1 xnor B1) and (not A0)and B0);
VLSI TECHNOLOGY
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Conclusion:
Grade
Lab-In-Charge
H.O.D.