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Exp4 Counter - Odt

The document contains VHDL code for a counter component and its testbench. The counter component uses a process to increment a signal called Pre_Q on each clock cycle when count is high, and resets it to 0 when clear is high. The testbench instantiates the counter, generates a clock signal, and runs 5 test cases to verify the counter increments and resets correctly. It checks for errors and reports the results.

Uploaded by

Daniel Gabriel
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
27 views

Exp4 Counter - Odt

The document contains VHDL code for a counter component and its testbench. The counter component uses a process to increment a signal called Pre_Q on each clock cycle when count is high, and resets it to 0 when clear is high. The testbench instantiates the counter, generates a clock signal, and runs 5 test cases to verify the counter increments and resets correctly. It checks for errors and reports the results.

Uploaded by

Daniel Gabriel
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
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Counter VHDL CODE

library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is generic(n: natural :=2); port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(n-1 downto 0) ); end counter; architecture behv of counter is signal Pre_Q: std_logic_vector(n-1 downto 0); begin -- behavior describe the counter process(clock, count, clear) begin if clear = '1' then Pre_Q <= Pre_Q - Pre_Q; elsif (clock='1' and clock'event) then if count = '1' then Pre_Q <= Pre_Q + 1; end if; end if; end process; -- concurrent assignment statement Q <= Pre_Q; end behv;

Counter Test Bench


library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity counter_TB is end counter_TB; architecture TB of counter_TB is component counter port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(1 downto 0) ); end component; signal T_clock: std_logic;

signal T_clear: std_logic; signal T_count: std_logic; signal T_Q: std_logic_vector(1 downto 0); begin U_counter: counter port map (T_clock, T_clear, T_count, T_Q); process begin T_clock <= '0'; wait for 5 ns; T_clock <= '1'; wait for 5 ns; end process; process variable err_cnt: integer :=0; begin T_clear <= '1'; T_count <= '1'; wait for 20 ns; T_clear <= '0'; -- start counting

-- clock cycle is 10 ns

-- clear output

-- test case 1 wait for 10 ns; assert (T_Q=1) report "Failed case 1" severity error; if (T_Q/=1) then err_cnt := err_cnt+1; end if; -- test case 2 wait for 10 ns; assert (T_Q=2) report "Failed case 2" severity error; if (T_Q/=2) then err_cnt := err_cnt+1; end if; -- test case 3 wait for 10 ns; assert (T_Q=3) report "Failed case 3" severity error; if (T_Q/=3) then err_cnt := err_cnt+1; end if; -- test case 4 wait for 10 ns; assert (T_Q=0) report "Failed case 4" severity error; if (T_Q/=0) then err_cnt := err_cnt+1; end if; -- test case 5 wait for 20 ns;

T_clear <= '1'; wait for 10 ns; assert (T_Q=0) report "Failed case 5" severity error; if (T_Q/=0) then err_cnt := err_cnt+1; end if; -- summary of all the tests if (err_cnt=0) then assert false report "Testbench of Adder completed successfully!" severity note; else assert true report "Something wrong, try again" severity error; end if; wait; end process; end TB;

RTL Schematic

Number of Slices: 2 Number of 4 input LUTs: 2 Number of bonded IOBs: 5

Timing Diagram

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