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Basic Verilog Programming Using Xilin Fpga

This document describes how to simulate basic Verilog programs using Xilinx ISE Spartan 3A software and verify them on an FPGA trainer kit. It outlines the steps to create a new project, add modules, synthesize, simulate using a test bench, and load/verify the program on the FPGA kit. It then provides examples of basic Verilog code for logic gates like AND, OR, XOR, and half/full adders as well as multiplexers and demultiplexers. The purpose is to simulate these basic Verilog programs using Xilinx tools and hardware.

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54 views

Basic Verilog Programming Using Xilin Fpga

This document describes how to simulate basic Verilog programs using Xilinx ISE Spartan 3A software and verify them on an FPGA trainer kit. It outlines the steps to create a new project, add modules, synthesize, simulate using a test bench, and load/verify the program on the FPGA kit. It then provides examples of basic Verilog code for logic gates like AND, OR, XOR, and half/full adders as well as multiplexers and demultiplexers. The purpose is to simulate these basic Verilog programs using Xilinx tools and hardware.

Uploaded by

antmonibritto
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
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BASIC VERILOG PROGRAMMING USING XILINX FPGA

Ex. no: Date: Aim:


To simulate the basic programs in VERILOG using Xilinx ISE Spartan 3A software and verify it using fpga trainer kit.

Procedure:
1. Open file->new project->give the project name and location to store it 2. Click next 3. Details of the software are opened selected the preferred language as VHDL/verilog and click next->finish 4. Right click the project->new source->VHDLmodule->give the project name which is created in step1.click next. 5. Then declare the inputs and output. 6. Click next->finish. 7. Program is created now the main line routine is typed and save the program 8. On the left side a tab is open double click synthesize 9. After synthesize is completed successfully we have to create a test bench for simulation. 10. Select simulation in the top left corner and right click the project->new source>VHDL/verilog test bench->give name for test bench->click next->finish 11. Test bench is created. 12. Select the test bench go to ISIM simulator->double click the simulate behavioral model 13. By changing the inputs in the test bench the required output is simulated. 14. Load the program in Xilinx Spartan ISE trainer with suitable output ports and verify the result.

Verilog programs: 1. AND:


Module and_1(a,b,c); Input a,b; Output c; Assign c=(a&b); End module;

2. OR:
Module or_1(a,b,c); Input a,b; Output c; Assign c=(a, b); End module;

3. XOR:
Module xor_1(a,b,c); Input a,b; Output c; Assign c=((~a& b)|(a &~b)); End module;

4. HALF ADDER:
Module half_adder (a,b,sum,carry); Input a,b; Output sum, carry; Assign sum=(~a& b)|(a &~b)); Assign carry=( a&b); End module;

5. FULL ADDER:
Modulehalf_adder (a,b,sum,carry); Input a,b,c; Output sum,carry; Assign sum=(a&(~b& ~c)|(b &c)|(~a&(~b& c)|(b&~c)); Assign carry=(b& c)|(a& b)|(a&~b& c); End module;

6. MUX:
Module mux-1(x,y,a,b,c,d,op); Input x,y,a,b,c,d; Output op; Assign op=((~x&~y& a)|(~x &y&b)|(x&~y& c)|(x&y&d)); End module;

7. DEMUX:
Module demux-1(e,i,x,y,a,b,c,d); Input,e, x,y,; Output a,b,c,d; Assign a=((e&i&(~x&~y )); Assign b=((e&i&(~x&~y )); Assign c=((e&i&(x&~y )); Assign d=((e&i&(x&y )); End module;

Result:
Thus the basic programs in verilog was simulated by using Xilinx Spartan ISE 3A software and verified in fpga trainer kit.

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