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Circuits and Svstems Letters

F. BILY

Abstract -A generalized switched-capacitor (SC) bistable circuit is presented. This bistable is used to implement a waveform generator capable of frequency and/or amplitude modulation. A technique of preventing the op amp of a SC amplifier from going to zero each clock cycle is described. The predicted performance is confirmed by experimental results.

l(b) and l(c) for a clockwise (CW) bistable and counterclockwise (CCW) bistable, respectively. A CW bistable characteristic is obtained when the +X and & of C,, are as shown in Fig. l(a). A CCW bistable is obtained when $x and +r of C,, are reversed. It can be observed that the bistable characteristics are completely general and can be shifted as desired by varying the appropriate V+, the capacitor ratios, and/or by changing $x or (p, of C,,. Simplified B&able Circuit

INTRODUCTION Switched-capacitor (SC) techniques have been used to implement analog circuits, other than filters, which are compatible with MOS integrated circuit technology [l]-[4]. This paper presents the results of using SC techniques to implement a waveform generator. The circuits used to implement the waveform generator are general and can be used for other analog integrated circuit applications. The contributions of this letter include a generalized bistable circuit, an inherent sample-and-hold (S/H) technique for SC amplifiers, and the use of the waveform generator for amplitude/frequency modulation. Generalized B&able Circuit A bistable is an important block in analog circuits. Recently, a SC bistable was presented which uses a differential, SC amplifier and a voltage comparator in a positive feedback configuration [4]. The input voltage and feedback voltage are sampled by capacitors and applied differentially to the SC amplifier. Fig. l(a) shows a generalized bistable circuit using SC circuits. The upper circuit, consisting of op amps 1 and 2, implements a SC amplifier with a S/H at the output and the ability to change the sign of the gain of the upper input depending upon the output of comparator 3. The inputs to the comparator are the bistable input and the output of the above amplifier, uTH. The lower circuit is similar to the upper amplifier. C, and C, are series SC realizations which simulate a resistor. The discrete time voltages, uTH, uc, and uoU,, are given as

The solid portion of Fig. 2 shows a simplified implementation of a CW bistable circuit based on the concepts of Fig. l(a). It can be shown that the second amplifier is not needed for a CW bistable characteristic with Vx = Vu = 0 and V, = VH. The output is taken at us and the input is applied at vT. The notation +X and $Ir implies these clocks are reversed depending upon the sign of v,. For the case of Fig. 2, (pX = +i and +r = e2 will give a noninverting gain. The phase reversal circuit is not shown but various types are described in [l], [2], and [4]. Fig. 2 uses a damped integrator configuration with a high cutoff frequency to replace the amplifier and S/H circuit of Fig. l(a). One of the objectives of this realization is to avoid having the output of the op amp slew to zero volts each time during the clock cycle. This SC configuration accomplishes this objective but cannot be a strays-insensitive configuration because of the phase reversal capability of the C,, input. This discrete-time transfer function from VA,, to V,,, can be expressed as -[sgnT$(z)](
v,T() =

2)

z-l

v,,,(z)

=+nV,(z)l(2) z-l
if C, = C{. C{ opposes the charge being transferred from C,, to C,. Only the charge difference on C,, between consecutive samples is transferred. As a result, the op amp output voltage changes only by the difference in the input voltage multiplied times the gain factor of the amplifier. Waveform Generator A waveform generator can be obtained by connecting a noninverting, SC integrator between us and ur. A voltage-controlled waveform generator can be obtained by connecting the dotted circuit shown in Fig. 2. A square wave will be generated at v, and a triangle wave at vz. The amplitude and frequency of the square and triangle waveforms are given as

v,,(z)= +-[sgnv,(z)] + v+ z-l i 1i 1 i = { ~,-bPv+mf)z-l V,(z)= {w[ VTdz)- vdz)l) v+

(1) (4

Fyi--[sgnV,(z)]2V+)z-
2 2

= {VT--[sgnV,(z)]VL}z-.

(3)

V is a positive voltage which is typically the positive power supply. The definitions implied in (l)-(3) are illustrated in the two output characteristics of the bistable circuit shown in Fig. and Manuscript receivedAugust 17, 1984. f = ( c,c31f,,ock) FREQ P. E. Allen is with the Schoolof Electrical Engineering,Georgia Institute of ox (6) Technoloev. Atlanta. GA 30332. (4GCll) UAMF . H. A. Rafat and s. F. Bily are with the Department of Electrical Engineering, Texas A & M University, CollegeStation, TX 77843. It is seen that the SC VCO in Fig. 2 is capable of amplitude 009%4094,85/0100-0103$01.00 01985 IEEE

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vOUT

! vx-vii

I 1 vx

I * vx+v, VIN

(b)
Fig. 1. (a) Generalized SC bistable circuit. (b) CW bistable characteristic.

(9 (c) CCW bistablecharacteristic. Experimental Results

Fig. 2. Simplified CW bistable circuit. The dotted portion is required for the wavefoorm generator implementation.

modulation (vary both vAMp and vFREQ simultaneously) and frequency modulation (vary only uFaaq). The range of variations of both amplitude and frequency is limited only by the imperfections of the op amps and comparator.

The circuit of Fig. 2 was constructed using 356 op amps and 201 CMOS switches. The clock frequency was 125 kHz. The capacitor values of Fig. 2 are Ci, = 0.3702 nF, C, =1.11952 nF, C,, = 2.591 nF, and C, = 27.44 nF. Fig. 3 shows the waveforms achieved from the circuit of Fig. 2. Fig. 3(a) is a photograph of the triangle and square waves with no modulation. The amplitude of the photograph is 2 V/div. and the time scale is 0.2 ms/div. uAMp was 7.5 V and vFREq was 2.0 V. The value of fclwk/fosc was 52.53. It was observed that the symmetry of the waveform generator was dependent upon the time constant of integration and the clock frequency. As ur- becomes greater (less) than us, the value of vc changes states. However, the actual change in the polarity of the integrator does not occur until the next clock cycle. If the ratio Of hock to f,,, is small, then this effect results in a noticeable lack of symmetry. If the ratio of fclock to f,,, happens to be just right, a jitter in the waveform of one clock period can occur if the clock frequency is not precise. These effects do not change the period of the waveform generator and as long as the ratio Of fclock to foscis high, they are unimportant. Fig. 3(b) shows the use of the waveform generator for amplitude modulation. The vertical scale is 1 V/div. and the horizontal scale was 2.0 ms/div. The clock frequency was changed to 128 kHz. A lOO-Hz sinusoid, offset for positive modulation, was

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ACKNOWLEDGMENT

The authors would like to acknowledge the help of Habib Golnabi in the testing of this circuit. REFERENCES P. E. Allen and E. SBnchez-Sinencio, SwifchedCupacirorCircuits. New York: Van Nostrand Reinhold, 1984,ch. 6-7. [2] K. Martin and A. S. Sedra, Switched-capacitor building blocks for adaptive systems, IEEE Trans. Circuits Syst., vol. CAS-28,pp. 576-584, June 1981. [3] F. Maloberti, Switched-capacitor building blocks for analogue signal processing,Electron. L&t., vol. 19, no. 7, pp. 263-265, Mar. 31, 1983. [4] B. J. Hosticka, W. Brockherde,U. Kleine, and R. Schweer,Design of nonlinear analog switched-capacitor circuits using building blocks, IEEE Trans. Circuits Sys~., vol. CAS-31,pp. 354-368, Apr. 1984. [l]

Pole Assignment of a Class of Multivariable Systems Using Localized Dynamic Output Compensators with Prescribed Poles
CHOO-MIN LIM
AND

S. ELANGOVAN

Abstract-A novel method for stabilizing a class of multivariable systems through pole assignment using decentralized dynamic compensators is presented. The method is particularly useful for designing stabilizers for improved dynamic stability of multimachine power systems; this is illustrated using a numerical example.

INTRODUCTION and effective method for designing output feedback dynamic compensator with prescribed poles to achieve exact assignment of the dominant pair of complex-conjugate eigenvalues for a class of SISO systems has been proposed [l]. Here the design method of [l] is generalized and extended to multivariable systems consisting of N subsystems. Within the framework of the proposed method, after repeated application of a matrix reduction technique, all the parameters of the N local output dynamic compensators are so determined to achieve exact (4 assignment of the system N dominant pairs of complex eigenvalFig. 3. (a) Photographof the squareand triangle waveforms.(b) Photograph ues to arbitrary locations in the s-plane. The effectiveness of the of the use of Fig. 2 for amplitude modulation. (c) Photographof the use of technique proposed is demonstrated using a multimachine power Fig. 2 for frequencymodulation. system. applied to both v,,, and uFREQ. A 100 percent modulation could be achieved. Fig. 3(c) shows the use of the waveform generator as a VCO. The vertical scale is 2 V/div. and the horizontal scale was 0.5 ms/div. A 470-Hz sinusoid superimposed on a dc offset was applied to v,,,o with vAMp held constant at 4.5 V. The range of frequency modulation was approximately three decades. It is necessary to apply an offset voltage to the amplifier in order to keep the waveforms symmetrical when vFREQ approached 0 V.
CONCLUSIONS A new, simple,

Problem Formulation Consider a multivariable tems

linear system consisting of N subsys-

k, = A;xi + B;u, + c Aijx, j=l

J$=[l

...

O] xi 9

B,=[O

...

bi]?

(1)

Let (1) represent a class of multivariable systems whose stability is governed predominantly by N pairs of complex-conjugate Manuscript receivedAugust 30, 1984. C. M. Lim is with the Electrical EngineeringDepartment, Ngee Ann Polytechnic, Singapore. S. Elangown is with the Electrical EngineeringDepartment, National University of Singapore,Singapore. 01985 IEEE

This paper has presented a SC waveform generator having the capability of amplitude or frequency modulation. Experimental data have confirmed the performance predicted in this paper. The results are indicative of the potential of SC circuits for analog integrated circuits. 0098-4094/85/0100-0105$01.00