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UNIVERSITY QUESTIONS
(May2003 to May2010)
Seme!e"# III Semester ECE S$%&e'! N(me# EC2203-Digital Electronics
)"e*("e+ ,-# S.RAMESH, Senior LecturerECE Ye(" # 20!0-20!! "## Semester
UNIT. I MINIMI/ATION TECHNIQUES AN0 LOGIC GATES
)ART.A
$- Re%eate# &uestion
1. I' A ( ) are )oolean *aria+les an# i' A,! ( A-),0, .in# )/
2. State DeMorgan0s t1eorem.$
3. E2%lain t1e term %rime im%licants.
1. A%%ly DeMorgan0s t1eorem to sim%li'y A-) C.
2. Sim%li'y A-A)-A-).
6. De'ine Ma2term ( Minterm. 3i*e e2am%les.
3. 4ro*e t1at A-A0),A-).
4. Mention any 2 a%%lications o' DeMorgan0s t1eorem.
5. E2%ress .,A-)0C as sum o' Minterm.
10. I' a manu'acturer s%eci'ies t1e minimum logical ! at a gate out%ut a 5.0* an# also s%eci'ies t1at
any *oltage #o6n u% to 3.7* 6ill +e consi#ere# as logical !. .in# t1e noise margin/
11. State t6o a#*antages o' CM"S logic.$
12. De'ine noise margin.
13. Determine t1e 'an-out gi*en I
IH8ma29
,50:A ( I
"H8ma29
,500:A.
11. ;1at are t1e a#*antages o' Sc1ott<y ==L 'amily/
12. ;1at are t1e uni*ersal gates/
16. De'ine 'an-in.
13. Dra6 t1e circuit #iagram o' a ==L >A>D gate.
14. ;1at are tri-state gates/
19. Reali?e ' , A6)-A)6 using minimum uni*ersal gates.
20. Dra6 a tri-state in*erter ( its trut1 ta+le.
21. ;rite #o6n 'an-in ( 'an-out o' a stan#ar# ==L IC.
22. ;1at is %ro%agation #elay o' gate/
23. Dra6 t1e logic #iagram 'or @, A)-)6C.
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24. Im%lement ., 8A)6-A)69 8C-D69 6it1 only >"R gate.
22. ;rite t1e )oolean 'unction o' an @"R gate gi*e its trut1 ta+le.
26. ;1at are o%en collector ( totem %ole out%uts/
23. Dra6 t1e @"R logic using only >A>D gates.
24. 4ro*e t1at t1e logical sum o' all minterms o' a )oolean 'unction o' 2 *aria+les is !.
25. S1o6 t1at a %ositi*e logic >A>D gate is a negati*e logic >"R gate.
30. Dra6 an acti*e 1ig1 tri-state +u''er ( 6rite its trut1 ta+le.
)ART.,
1. .in# a minimal S"4 re%resentation 'or '8A,),C,D,E9,A
m
8!,5,7,!0,20,22,25,279-#80,!!,!7,2B9
using C-ma% met1o#. Dra6 t1e circuit o' t1e minimal e2%ression using only >A>D. 8!79
2. 4ro*e t1at 82
!
-2
2
9 82
!0
2
30
-2
3
9 82
20
-2
!
2
3
90 , 2
!
2
2
. 8D9
3. E2%ress t1e s6itc1ing 'unction ' 8)A9 , A in terms o' Minterm. 8D9
4. Sim%li'y t1e E *aria+le s6itc1ing 'unction '8EDC)A9,A
m
83,E,7,D,F,!2,!3,!5,!F,22,25,2E,309.
8!79
5. Sim%li'y using C-ma% to o+tain minimum 4"S e2%ression 8A0-)0-C-D9 8A-)0-C-D9
8A-)-C-D09 8A-)-C0-D09 8A0-)-C-D09 8A-)-C0-D9. 8!79
6. 4lot t1e e2%ression on t1e C-ma% .86,2,y9 , A80,!,2,3,E,79 - #82,59. 8!79
7. 4ro*e t1e %er'ect in#uction 8i9A-A),A 8ii9A-A0),A-) 8iii9A8A-)9 ,A 8i*9A8A0-)9 ,A).8D9
4. Re#uce t1e 'ollo6ing 'unction using C,ma%, ',A)C0-A0)0C-A)C-A)0C ( reali?e using only
>A>D. 8D9
5. List out t1e +asic rules 8la6s9 t1at are use# in )oolean alge+ra e2%ressions 6it1 e2am%le.$8D9
10. ;rite t1e ste%s 'or sim%li'ying a logic e2%ression using a C-ma%. 8!09
11. 8i9 Sim%li'y using C-ma% @,A0)-A0)0C-A)C0-A)0C0. 8ii9 Con*ert S"4 to eGui*alent
4"S A0)0C-A0)0C-A0)C-A)0C-A)C. 8iii9 A%%ly DeMorgan0s t1eorem H8A-)-C9 DI6.
8i*9Jsing )oolean rules ( la6s sim%li'y K, 8A0-)9 8A-)9.
8!79
12. 4ro*e t1e 'ollo6ing using DeMorgan0s t1eorem, A)-CD,88A)90. 8CD9090 ( 8A-)9
8C-D9 ,88A-)90-8C-D9090.
8D9
13. Con*ert 8A-)9 8A-C9 8)-C09 into stan#ar# 4"S 'orm.
8D9
14. Minimi?e t1e 5 *aria+le logic 'unction using C-ma%, '8A,),C,D9,
A
m
80,!,2,3,E,B,D,F,!!,!59. 8!09
12. "+tain t1e Canonical 4"S 'or .8A,),C9,8A-)098)-C98A-C09. 879
16. Jsing t1e C-ma% met1o# o+tain t1e minimal S"4 ( 4"S e2%ressions 'or t1e 'unction .82,y,?,69
,A8!,3,5,E,7,B,F,!2,!39. 8!09
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17. A%%ly DeMorgan0s t1eorem 'or t1e 'unction L8A-)-C9 DM0.
839
14. .in# t1e com%lement o' A-)C-A). 839
19. Re#uce t1e 'ollo6ing 'unction using C-ma% tec1niGue .8A,),C,D9, A
m
8E,7,B,!2,!39-
A
#
85,F,!5,!E9. 8D9
20. Sim%li'y t1e 'ollo6ing e2%ression using )oolean alge+ra .82,y,?,9 ,N
m
83,E,B9.
8D9
21. E2%lain t1e 6or<ing o' a +asic totem-%ole ==L 2 in%ut >A>D gate.$ 8D9
22. E2%lain t1e termsO .an-in, .an-out, =ri-state gates, ( 4ro%agation #elay. 8D9
23. E2%lain t1e 6or<ing o' 2 in%ut CM"S >A>D gate. ;1at are t1e c1aracteristics o' CM"S.8!09
21. Dra6 t1e circuits o' 2 in%ut >A>D ( 2 in%ut >"R gate using CM"S.$ 8D9
22. "+tain 3 le*el >"R->"R im%lementation o' ' 8a, +, c, #, e, '9 , 8a+-c#9 e'. 8D9
26. E2%lain 6it1 a circuit t1e 6or<ing o' 3 state ==L gate.$
8D9
27. Minimi?e ' 8A, ), C, D, E9 ,P
M
82, 5, B, F, 27, 2D, 2F, 3!9, im%lement t1e resultant
'unction using >"R only.
8!79
24. E2%lain t1e 6or<ing o' CM"S logic gates. 8D9
29. Im%lement t1e 'ollo6ing 'unction using a Gua# 2 in%ut >"R gates, ', 8A6)-C9.D6.
8D9
30. Dra6 a ==L gate t1at gi*es an out%ut 8A)96 ( e2%lain its o%eration.
8D9
31. Dra6 t1e sym+ol, trut1 ta+le ( t1e eGuation o' t1e 3 +asic gates ( 2 uni*ersal gates an# reali?e
all t1e E gates using eit1er o' t1e uni*ersal gates. 8!79
32. Enumerate t1e %recautionary measures to +e consi#ere# 61ile 1an#ling CM"S #e*ices.$ 8E9
33. List out ( e2%lain t1e #ata s1eet %arameters. 8!!9
31. Im%lement t1e e2%ression 8i9 A)-)CD-E.3H 8ii9 8A-)9 8C-D-E9 8.-3-H-I9 6it1 logic
gates.
35. Sim%li'y ( #ra6 logic #iagram 'or t1e e2%ression, Q, C.).A- C.).A- C.).A.
36. Dra6 t1e logic sym+ol o' @->"R gate ( gi*e its trut1 ta+le. 859
33. E2%lain t1e o%eration o' 3 in%ut ==L >A>D gate 6it1 reGuire# #iagram ( trut1 ta+le. 8D9
34. E2%lain t1e o%eration o' CM"S >A>D ( >"R gates 6it1 t1e circuits ( trut1 ta+le. 8D9
39. Com%are ( contrast t1e 'eatures o' ==L ( CM"S logic 'amilies.$
8D9
10. E2%ress t1e )oolean 'unction .,@Q-@0K in %ro#uct o' ma2term. 879
41. Re#uce t1e 'ollo6ing 'unction using C-ma% tec1niGue '8A)CD9,
N80,3,5,B,D,!0,!2,!59-#82,79.
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8!09
42. Sim%li'y t1e 'ollo6ing 'unction using &uine McClus<ey met1o# .8A)CD9,A
80,2,3,7,B,D,!0,!2,!39 8!79
43. Minimi?e t1e term using &uine McClus<ey met1o# ( *eri'y t1e result using C-ma%
met1o# NM80,!,5,!!,!3,!E9- N#8E,B,D9.
8!29
11. E2%ress t1e )oolean 'unction as 8i94"S 'orm 8ii9S"4 'orm D,8A0-)98)0-C9 859
45. Im%lement t1e 'ollo6ing 'unction using >"R gates.
8D9
"ut%ut,! ;1en t1e in%uts are Am 80,!,2,3,59("ut%ut,0 ;1en t1e in%uts are Am 8E,7,B9
UNIT II COM,INATIONAL CIRCUITS
)ART.A
$- Re%eate# &uestion
1. ;1at is a De-Mu2/
2. ;1at is com+inational circuit/ 3i*e e2am%les.
3. Dra6 t1e 'lo6 #iagram o' 3ray to )inary con*ersion.
1. Re%resent a 1al' a##er in +loc< #iagram 'orm ( also its logic im%lementation.
2. ;1at are t1e maRor categories o' logic circuits/
6. ;rite t1e )oolean e2%ression 'or t1e out%ut o' t1e system.
3. ;rite t1e trut1 ta+le o' a 5O! Mu2.
4. E2%ress 3ray co#e !0!!!into +inary num+ers.
9. Con*ert 837B9
!0
into E2cess 3 Co#e.
10. Suggest a solution to o*ercome t1e limitation on t1e s%ee# o' an a##er.
11. Di''erentiate #eco#er 'rom #emulti%le2er.
12. ;rite an e2%ression 'or +orro6 ( #i''erence in a 'ull su+tractor circuit.
)ART.,
1. State t1e con#ition 'or ), I
2
in )oolean e2%ression ), I
0
S
0
0 S
!
0 - I
!
S
0
0 S
!
- I
2
S
0
S
!
0- I
3
S
0
S
!
.
;1at is t1e com+inational logic circuit reali?e# +y t1e a+o*e )oolean e2%ression/ 8!79
2. State t1e con#ition to c1ec< t1e eGuality o' t6o n-+it +inary num+ers A ( ). 8D9
3. Design a 'ull a##er ( a 'ull su+tractor. 8!09
1. Dra6 t1e +loc< #iagram o' a 20s com%lement a##ersu+tractor. 8D9
2. Design ( e2%lain t1e 6or<ing o' a ! to D De-Mu2. 8D9
6. Dra6 a circuit o' 2 to ! Mu2 ( ! to 2 De-Mu2. 859
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3. Design ( e2%lain t1e 'ollo6ing circuits, 8i9 Com%arator 8ii9 5 to ! Mu2. 8!79
4. Design a loo< a1ea# carry generator. 8D9
5. Reali?e .86, 2, y, ?9, S 8!,5,7,B,D,F,!0,!!,!E9 using D to ! Mu2. 8D9
10. Design a )CD to 3ray co#e con*erter. Jses #on0t care. 8!09
11. E2%lain carry loo< a1ea# a##er circuit.$ 8D9
12. Design ( e2%lain t1e 6or<ing o' a #eco#er. 8D9
13. Design ( e2%lain t1e 6or<ing o' 3ray to )CD con*erter.$
8D9
11. ;1at is t1e sim%lest logic circuit 'or a #eco#er t1at %ro#uces a T!0 out%ut 61en )CD in%ut is
T00000/ 8D9
12. Dra6 t1e #iagram ( e2%lain ! to !7 De-Mu2 circuit. 8D9
16. Im%lement 'ull a##er using 2 1al' a##er. 8D9
13. Dra6 ( e2%lain t1e )CD a##er circuit. 8D9
14. Design a E +it com%arator using single ICB5DE ( a gate. 8D9
15. Im%lement t1e 'unction 6it1 a multi%le2er .8A,),C, D9 ,A80,!,3,5,D,F,!E9. $ 879
20. E2%lain t1e o%eration o' a 5 +it magnitu#e com%arator. 8!09
21. E2%lain e*en %arity c1ec<er. 879
22. E2%lain t1e %roce#ure 'or con*erting +inary to 3ray co#e num+er ( 3ray to +inary
num+er 6it1 e2am%le.
8D9
23. Im%lement 'ull su+tractor using #emulti%le2er.
8!09
24. Im%lement t1e gi*en )oolean 'unction using DO! multi%le2er .8A,),C9 ,A8!,3,E,79.$
879
25. Deri*e t1e eGuation 'or a 5-+it loo< a1ea# carry a##er circuit.$
879
26. Dra6 ( e2%lain t1e +loc< #iagram o' a 5-+it serial a##er to a## contents o' t6o registers.
8!09
27. Multi%ly 8!0!!9
2
+y 8!!0!9
2
using a##ition an# s1i'ting o%eration also #ra6 +loc<
#iagrams o' t1e 5 +it +y 5 +it %arallel multi%lier.
8D9
28. Design ( im%lement t1e con*ersion circuits 'or )inary co#e to 3ray co#e.
8D9
---------
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UNIT. III SEQUENTIAL CIRCUIT
)ART.A
1. ;1at is t1e con#ition on UC .. to 6or< as D ../
2. Con*ert a D .. into a = ...
3. ;rite t1e c1aracteristic eGuation o' a UC ...
1. Deri*e = .. 'rom UC ...
2. Dra6 t1e logic #iagram o' SR ...
6. ;1at is meant +y ma2imum allo6a+le cloc< s<e6/
3. ;1at is a seGuential circuit/ 3i*e an e2am%le.
4. >ame t6o seGuential s6itc1ing circuits.
5. ;1at is t1e #ra6+ac< o' SR ../ Ho6 is t1is minimi?e#/
10. ;1at is an async1ronous seGuential circuit/
11. Ho6 #oes a UC .. #i''er 'rom an SR .. in its +asic eGuation/
12. Dra6 a scale o' D-+it ri%%le counter.
13. De'ine sync1ronous counter.
11. ;1at is a seGuence generator/
12. I' a SIS" s1i't register 1as > stages an# i' t1e cloc< 'reGuency is T'0, 61at 6ill +e t1e time #elay
+et6een i% ( o%/
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16. Dra6 t1e timing #iagram o' 5-+it ring counter.
13. Dra6 a 2-+it ri%%le counter (Con*ert t1is into a 2-+it ring counter.
14. Classi'y t1e registers 6it1 res%ect to serial ( %arallel in%ut out%ut.
15. Dra6 t1e logic sym+ol an# trut1 ta+le o' a D ..
20. ;1at is race aroun# con#ition/
21. Con*ert =-.. into an SR-... Dra6 t1e circuit.
22. Dra6 t1e state #iagram o' M"D-!0 counter.
23. Dra6 t1e gate le*el logic #iagram o' MS-UC-...
21. ;rite #o6n t1e c1aracteristic eGuation 'or UC 'li%-'lo%.
25. Distinguis1 +et6een sync1ronous ( a sync1ronous seGuential circuits.
26. Mention any 2 #i''erences +et6een t1e e#ge triggering ( le*el triggering.
23. ;1at is meant +y %rogramma+le counter/ Mention its a%%lications.
)ART.,
1. E2%lain t1e 6or<ing MasterSla*e UC ...$
2. Design ( e2%lain t1e 6or<ing o' an J4-D";> ri%%le counter.
3. E2%lain t1e 6or<ing o' )CD ri%%le counter 6it1 timing #iagrams.$
1. Design an# e2%lain t1e 6or<ing o' a M"D-!! counter.
2. Design an# e2%lain t1e 6or<ing o' a sync1ronous M"D-3 counter.
6. Design an# e2%lain t1e 6or<ing o' a sync1ronous M"D-B counter.
3. ;rite notes on state minimi?ation.
4. Design a sync1ronous counter 6it1 states 0, !, 2, 3, 0, !,...using UC ...
5. Dra6 an async1ronous #eca#e counter ( e2%lain its o%eration 6it1 neat 6a*e'orms.
10. Dra6 a 3-+it re*ersi+le counter ( e2%lain its o%eration 6it1 neat 6a*e'orms.
11. Dra6 a 7-stage ring counter ( e2%lain its o%eration. Mention t1e use o' t1e counter.
12. Dra6 a E .. s1i't counter, its trut1 ta+le ( 6a*e'orms. E2%lain its o%eration as a #eca#e
counter.
13. Dra6 a 5-+it SIS" s1i't register ( #ra6 its 6a*e'orms
11. Dra6 t1e 5-+it Uo1nson counter ( e2%lain t1e o%eration.
12. Dra6 a D-+it SI4" s1i't register ( E2%lain t1e o%eration.
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16. Design a 3-+it +inary counter using = .. t1at 1as a re%eate# seGuence o' 7 states. 000-00!-0!0-
0!!-!00-!0!-!!0. 3i*e t1e state ta+le, state #iagram ( logic #iagram.
13. Dra6 t1e cloc<e# RS .. ( E2%lain 6it1 trut1 ta+le.
14. Dra6 t1e logic #iagram 'or a E- +it serial loa# s1i't register using D .. ( e2%lain.
15. Dra6 t1e logic #iagram 'or a 5- +it %arallel loa# recirculating s1i't register. ( e2%lain.
20. Design a 3- +it sync1ronous counter using UC ...
21. Design a 3- +it +inary counter ( 6rite t1e trut1 ta+le ( o% 6a*e'orm
22. Design a E-+it s1i't register using E Master sla*es ...
23. Dra6 t1e logic #iagram o' a D-.. using >A>D gates ( e2%lain.
21. ;it1 a neat circuit #iagram e2%lain a uni*ersal s1i't register.$
22. Design a 3 +it async1ronous ri%%le counter using =..s ( e2%lain its o%eration.
26. Ho6 6ill you con*ert a D 'li%-'lo% into UC 'li%-'lo%/
23. ;1at is meant +y uni*ersal s1i't register/ E2%lain t1e %rinci%le o' o%eration o' 5-+it uni*ersal
s1i't register.
24. ;rite #o6n t1e c1aracteristic ta+le 'or UC 'li%-'lo% 6it1 >"R gates.
25. Design a 2 +it sync1ronous J%Do6n counter.
30. Realise UC 'li%-'lo% using SR 'li%-'lo%.
-----
UNIT. IV MEMORY 0EVICES
)ART.A
1. ;1at is an E4R"M/
2. ;1ic1 memory is calle# *olatile/ ;1y/
3. Dra6 t1e +asic #ynamic memory cell.
1. ;1at is meant +y static ( #ynamic memories/
2. Ho6 is t1e in#i*i#ual location in an E4R"M %rogramme# 8or9 erase#/
6. E2%lain static memory/
3. ;1at is a RAM/
4. Mention 2 ty%es o' erasa+le 4R"M.
5. ;1at is memory #eco#ing/
10. ;1et1er R"M is classi'ie# as a non *olatile storage #e*ice/ ;1y/
11. ;rite t1e a#*antage o' E4R"M o*er a 4R"M.
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12. Dra6 t1e logic #iagram o' memory cell.
13. ;1at is a com+inational 4LD/
11. ;1at is 6rite cycle time/
12. E2%lain E4R"M/
16. List t1e a#*antages o' 4LD0s.
13. E2%lain 6rite o%eration 6it1 an e2am%le.
14. Dra6 +loc< #iagram o' Dynamic RAM cell.
15. ;1at is a memory cycle/
20. Com%are 'eatures o' 4R"M, 4AL an# 4LA.
21. Com%are ( contrast static RAM ( #ynamic RAM.
22. ;1at is 4AL/ Ho6 #oes it #i''er 'rom 4LA/
23. ;1at are t1e a#*antages o' static RAM com%are# to #ynamic RAM/
21. ;1at is meant +y memory e2%ansion/ Mention its limit.
)ART.,
1. ;rite notes on R"M, E4R"M, an# 4LA. 8!09
2. Dra6 a RAM cell an# e2%lain its 6or<ing. 8D9
3. Descri+e t1e RAM organi?ation. 8D9
1. A )i%olar RAM c1i% is arrange# as !7 6or#s. Ho6 many +its are store# in t1e c1i%/ 859
5. ;rite note on M"S.E= RAM cell. 8D9
6. ;rite note on Dynamic RAM cell. 8D9
7. Ho6 can one ma<e 75@D R"M using 32@5 R"Ms/ Dra6 suc1 a circuit ( e2%lain. 8!09
4. Dra6 a #ynamic RAM cell ( e2%lain its o%eration. Com%are its sim%licity 6it1 t1at o' >M"S
static RAM cell, +y 6ay o' #iagram ( o%eration. 8!79
9. Illustrate t1e conce%t o' !7@D +it R"M arrangement 6it1 #iagram. 8!09
10. E2%lain t1e +asic structure o' a 2E7@5 static RAM 6it1 neat #iagram. 8!09
11. Descri+e t1e ty%ical R"M internal organi?ation 6it1 neat #iagram.
8D9
12. Ela+orate t1e single 'use# 4R"M cell 6it1 clear s<etc1. 879
13. Categories RAM ( R"M an# e2%lain in #etail.
8!79
14. E2%lain t1e 'ollo6ing termsO Dynamic memory, *olatile storage, .iel# %rogramma+le,
Mas< %rogramma+le. 8!79
12. ;rite s1ort notes on RAM, ty%es o' R"Ms. 8!79
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16. Im%lement t1e 'ollo6ing 2 )oolean 'unctions 6it1 4LA.8i9 .
!
8A,),C9,A80,!,2,59 8ii9
.
2
8A,),C9, A80,E,7,B9.
8!79
13. Dra6 t1e +loc< #iagram o' a 4LA #e*ice ( +rie'ly e2%lain eac1 +loc<. 8!79
18. Design a !7+it R"M array ( e2%lain t1e o%eration.
8D9
15. ;rite s1ort notes on .43A.$ 879
20. E2%lain 8i9 Memory #eco#ing 8ii9 E2%lain t1e *arious R"M organi?ations an# gi*e t1e
uses 'or eac1 ty%e.
8!09
21. A com+inational circuit #e'ine# +y 'unctions .
!
8A,),C9,A83,E,7,B9 an# .
2
8A,),C9,
A80,2,5,B9.Im%lement t1e circuit 6it1 a 4LA 1a*ing 3 in%uts, 5 %ro#uct terms an# 2 out%uts. 8!79
22. 3i*e t1e classi'ication o' semicon#uctor memories. 8D9
23. ;rite s1ort notes on E4R"M an# EE4R"M. 8D9
21. E2%lain t1e rea# cycle an# 6rite cycle timing %arameters 6it1 t1e 1el% o' timing #iagrams. 8D9
25. Im%lement t1e 'ollo6ing )oolean 'unctions 6it1 4LA.8i9 .
!
8A,),C9,A80,!,2,59 8ii9
.
2
8A,),C9, A80,E,7,B9 8iii9 .
3
8A,),C9, A80,3,E,B9.
8!79
26. Design a com+inational circuit using R"M. =1e circuit acce%ts a t1ree +it num+er (
out%uts a +inary num+er eGual to t1e sGuare o' t1e in%ut num+er.
8!79
23. E2%lain t1e %rinci%le o' o%eration o' )i%olar SRAM cell. 8D9
24. A com+inational circuit is #e'ine# as t1e 'unctions .!,A)0C0-A)0C-A)C (
.2,A0)C-A)0C-A)C. Im%lement t1e #igital circuit 6it1 a 4LA 1a*ing 3 in%uts, 3 %ro#uct
terms an# 2 out%uts. 8D9
-----
UNIT. V SYNCHRONOUS AN0 AYNCHRONOUS SEQUENTIAL CIRCUITS
)ART.A
1. ;1at is a 'un#amental mo#e seGuential circuit/
2. De'ine cycle.
3. ;1at is an Async1ronous SeGuential Circuit/
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1. De'ine a sta+le state.
2. ;1at is t1e cause 'or essential Ha?ar#/
6. De'ine static Ha?ar#/
3. ;1en #o Ha?ar#s occur/
4. De'ine state assignment/
9. ;1at is race/$
10. ;1at is a 'lo6 ta+le/
11. ;1at is e2citation ta+le/
12. De'ine Ha?ar#/$
13. E2%lain Dynamic Ha?ar#.
11. De'ine static Ha?ar#. Ho6 it can +e a*oi#e#/
12. ;1at are Ha?ar#s/
16. Com%are t1e ASM c1art 6it1 a con*entional 'lo6 c1art.
13. Dra6 +loc< #iagram 'or Moore mo#el.
14. ;1at are t1e 1a?ar# 'ree #igital circuits/
)ART.,
1. Design an async1ronous seGuential circuit 6it1 2 i%s @ ( Q an# 6it1 one o% K. ;1ene*er Q is T!0,
i% @ is trans'erre# to K. ;1en Q is 0, t1e o% #oesn0t c1ange 'or any c1ange in @. Jse t1e SR latc1
im%lementation o' t1e circuit.
2. ;rite notes on t1e 'ollo6ing gi*ing one e2am%le 'or eac1. 8i9.Sta+le state 8ii9.Jnsta+le state 8iii9
Cycle 8i*9 races.
3. "+tain t1e 4rimiti*e 'lo6 ta+le 'or an async1ronous circuit t1at 1as 2 i%s @ an# Q ( o% K. An o% K
,! is to occur only #uring t1e i% state @Q,0! ( t1en i' an# only i' t1e i% state @Q,0! is %rece#e# +y
t1e i% seGuence @Q,0!, 00, !0, 00, !0, 00.
1. E2%lain Races an# 1a?ar#s 6it1 suita+le e2am%les.
2. Design a circuit 6it1 %rimary i% A ( ) to gi*e an o% K,!, 61en A +ecomes T!0 i' ) is alrea#y !.
"nce K,! it 6ill remain so until A goes to 0.Dra6 6a*e'orm #iagram, total state #iagram, 4rimiti*e 'lo6
ta+le 'or #esigning t1is circuit. 8!79
6. Discuss met1o#s o' #esigning race 'ree ( Ha?ar# 'ree circuits 6it1 e2am%les.$
3. Dra6 t1e 'un#amental mo#e async1ronous circuit ( e2%lain in #etail. 8D9
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4. Illustrate 4ulse mo#e async1ronous circuit. 8D9
5. De'ine 'ollo6ing terms i9 Critical race ii9 >on critical race iii9 .lo6 ta+le i*9 Ha?ar#
10. Illustrate mi2e# o%erating mo#e seGuential circuit mo#el. 8D9
11. ;rite note on Ha?ar#. 8D9
12. ;1at are 1a?ar#s/ E2%lain in #etail 6it1 a suita+le e2am%le/$ 8!79
13. =1e circuit 1as 2 i%s = 8toggle9 ( C 8cloc<9 ( one o% &. =1e o% state is com%lemente# i' =,! ( C
c1anges 'rom ! to 08-*e e#ge triggering9 ot1er6ise, un#er any ot1er i% con#ition, t1e o% & remains
unc1ange#. Deri*e t1e %rimiti*e 'lo6 ta+le an# im%lication ta+le. 8!79
11. Design an async1ronous circuit using UC .. t1at 6ill %ro#uce o% only t1e 'irst %ulse recei*e# an#
6ill ignore any ot1er %ulses. 8!79
12. Design an async1ronous circuit t1at 6ill o% only t1e 'irst %ulse recei*e# 61ene*er a control i% is
asserte# 'rom lo6 to 1ig1 state. Any 'urt1er %ulses 6ill +e ignore#. 8!79
16. Design =-.. gi*ing t1e 'lo6 ta+le, state ta+le, state assignment, e2citation ta+le an# e2citation ma%.
8!79
13. Design a t1ree +it +inary counter using = 'li%-'lo%s. 8!79
14. Design a negati*e-e#ge triggere# = 'li%-'lo%. 8!79
15. ;1at are calle# as essential 1a?ar#s/ Ho6 #oes t1e 1a?ar# occur in seGuential circuits/ Ho6 can t1e
same +e eliminate# using SR latc1es/ 3i*e an e2am%le. 8!79
--------
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