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Hef 4001 Quadruple Input

This document provides data on the HEF4001B quadruple 2-input NOR gate integrated circuit, including: - It describes the HEF4001B as providing four independent 2-input NOR functions with fully buffered outputs for noise immunity. - Pinout diagrams and packaging/lead options including plastic and ceramic DIL packages are shown. - Timing characteristics like propagation delays and output transition times are provided across voltage and temperature ranges. - Formulas for estimating power dissipation under different operating conditions are given.

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44 views

Hef 4001 Quadruple Input

This document provides data on the HEF4001B quadruple 2-input NOR gate integrated circuit, including: - It describes the HEF4001B as providing four independent 2-input NOR functions with fully buffered outputs for noise immunity. - Pinout diagrams and packaging/lead options including plastic and ceramic DIL packages are shown. - Timing characteristics like propagation delays and output transition times are provided across voltage and temperature ranges. - Formulas for estimating power dissipation under different operating conditions are given.

Uploaded by

wlen2012
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4001B gates Quadruple 2-input NOR gate


Product specication File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specication

Quadruple 2-input NOR gate


DESCRIPTION The HEF4001B provides the positive quadruple 2-input NOR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.

HEF4001B gates

Fig.2 Pinning diagram.

HEF4001BP(N): HEF4001BD(F): HEF4001BT(D):

14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1)

( ): Package Designator North America Fig.1 Functional diagram.

Fig.3 Logic diagram (one gate).

FAMILY DATA, IDD LIMITS category GATES See Family Specications

January 1995

Philips Semiconductors

Product specication

Quadruple 2-input NOR gate


AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 60 25 20 50 25 20 60 30 20 60 30 20 120 50 40 100 45 35 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP MAX

HEF4001B gates

TYPICAL EXTRAPOLATION FORMULA 33 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 23 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL

VDD V Dynamic power dissipation per package (P) 5 10 15

TYPICAL FORMULA FOR P (W) 1100 fi + (foCL) VDD2 5000 fi + (foCL) 14 200 fi + (foCL) VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)

January 1995

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