System Programming

System Software: An Introduction to Systems Programming

Book

Course Information

Time

7:10pm to 10:00pm on Monday.

Web Sites

http://140.128.101.171/~johnaxer
[email protected] http://www.hpc.csie.thu.edu.tw

Teachers email address

Teaching assistant

Gain Score

Participation: 5 % Two quizzes: 20% Two or Three home works: 15 % A final project: 15% A mid exam: 20% A final exam: 25%

System Programming

Chapter 1: Background Chapter 2: Assemblers Chapter 3: Loaders and Linkers Chapter 4: Macro Processors Chapter 5: Compilers
Operating Systems Other System Software Software Engineering Issues

Chapter 1 Background

Outline

Introduction System Software and Machine Architecture The Simplified Instructional Computer (SIC)

SIC Machine Architecture SIC/XE Machine Architecture SIC Programming Examples

Traditional (CISC) Machines RISC Machines

1.1 Introduction

System Software consists of a variety of programs that support the operation of a computer. The programs implemented in either software and (or) firmware that makes the computer hardware usable. The software makes it possible for the users to focus on an application or other problem to be solved, without needing to know the details of how the machine works internally.

BIOS (Basic Input Output System)

1.2 System Software and Machine Architecture

System Software vs Application

One characteristic in which most system software differs from application software is machine dependency. System programs are intended to support the operation and use of the computer itself, rather than any particular application. Text editor, assembler, compiler, loader or linker, debugger, macro processors, operating system, database management systems, software engineering tools,
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Examples of system software

1.2 System Software and Machine Architecture

Text editor

To create and modify the program

Compiler and assembler

You translated these programs into machine language

Loader or linker

Debugger

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System Software Concept

Application Program
Debugger Complier Macro Processor Text Editor Utility Program (Library) Load and Linker

Assembler

Memory Management

Process Management

Device Management

Information Management

OS

Bare Machine (Computer)

System Software and Machine Architecture

Machine dependent ()

Instruction Set, Instruction Format, Addressing Mode, Assembly language General design logic/strategy, Two passes assembler

Machine independent ()

Machine independent
Machine Dependent
Computer

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1.3 The Simplified Instructional Computer

Like many other products, SIC comes in two versions

The standard model An XE version

extra equipments, extra expensive

The two versions has been designed to be upward compatible SIC (Simplified Instructional Computer) SIC/XE (Extra Equipment)

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1.3 The Simplified Instructional Computer

SIC

Upward compatible Memory consists of 8-bit bytes, 3 consecutive bytes form a word (24 bits) There are a total of 32768 bytes (32 KB) in the computer memory. 5 registers, 24 bits in length

A X L PC SW

0 1 2 8 9

Accumulator Index register Linkage register (JSUB) Program counter Status word (Condition Code)

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1.3.1 SIC Machine Architecture

Data Formats

Integers are stored as 24-bit binary number 2s complement representation for negative values Characters are stored using 8-bit ASCII codes No floating-point hardware on the standard version of SIC

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Instruction Cycle

CPU

Control Unit (CU) Arithmetic and Logic Unit (ALU) Register Fetch Cycle Execution Cycle

Instruction Cycle

Fetch Instruction

Decoder

Fetch Operand

Computation

Store Result

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1.3.1 SIC Machine Architecture

Instruction format

24-bit format The flag bit x is used to indicate indexed-addressing 15 1 8 mode

Addressing Modes

There are two addressing modes available

Indicated by x bit in the instruction (X) represents the contents of reg. X

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1.3.1 SIC Machine Architecture

Instruction set

Format 3 Load and store registers (LDA, LDX, STA, STX, etc.) Integer arithmetic operations (ADD, SUB, MUL, DIV) Compare instruction (COMP) Conditional jump instructions (JLT, JEQ, JGT) JSUB jumps to the subroutine, placing the return address in register L. RSUB returns by jumping to the address contained in register L.

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1.3.1 SIC Machine Architecture

I/O

I/O are performed by transferring 1 byte at a time to or from the rightmost 8 bits of register A. Each device is assigned a unique 8-bit code as an operand. Test Device (TD): tests whether the addressed device is ready to send or receive

< ready

= not ready

Read Data (RD) Write Data (WD)

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1.3.2 SIC/XE Machine Architecture

1 megabytes (1024 KB) in memory 3 additional registers, 24 bits in length

B S T

3 4 5

Base register; used for addressing General working register General working register

1 additional register, 48 bits in length

Floating-point accumulator (48 bits)

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1.3.2 SIC/XE Machine Architecture

Data format

24-bit binary number for integer, 2s complement for negative values 48-bit floating-point data type The exponent is between 0 and 2047 f*2(e-1024) 0: set all bits to 0
1 S 11 36

exponent

fraction

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1.3.2 SIC/XE Machine Architecture

Instruction formats

Relative addressing () - format 3 (e=0) Extend the address to 20 bits - format 4 (e=1) Dont refer memory at all - formats 1 and 2

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1.3.2 SIC/XE Machine Architecture

Addressing modes

n i x b p e Simple n=0, i=0 (SIC) or n=1, i=1 Immediate n=0, i=1 TA=Valus Indirect n=1, i=0 TA=(Operand) Base relative b=1, p=0 TA=(B)+disp 0 <= disp <= 4095 PC relative b=0, p=1 TA=(PC)+disp -2048 <= disp <= 2047

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1.3.2 SIC/XE Machine Architecture

Addressing mode

Direct Index Index+Base relative Index+PC relative Index+Direct Format 4

b=0, p=0 TA=disp x=1 TAnew=TAold+(X) x=1, b=1, p=0 TA=(B)+disp+(X) x=1, b=0, p=1 TA=(PC)+disp+(X) x=1, b=0, p=0 e=1

Appendix and Fig. 1.1 Example

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Figure 1.1

Memory address

00000 ~FFFFF (Byte)

(0000 0000 0000 0000 0000)

(1111 1111 1111 1111 1111)

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1.3.2 SIC/XE Machine Architecture

Instruction set

Format 1, 2, 3, or 4 Load and store registers (LDB, STB, etc.) Floating-point arithmetic operations (ADDF, SUBF, MULF, DIVF) Register-to-register arithmetic operations (ADDR, SUBR, MULR, DIVR) A special supervisor call instruction (SVC) is provided 1 byte at a time, TD, RD, and WD SIO, TIO, and HIO are used to start, test, and halt the operation of I/O channels.
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I/O

1.3.3 SIC Programming Examples

Sample data movement operations

No memory-to-memory move instructions (Fig. 1.2)

five

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

Sample arithmetic operations

(ALPHA+INCR-1) assign to BETA (Fig. 1.3) (GAMMA+INCR-1) assign to DELTA

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

String copy

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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Traditional (CISC) Machines

Complex Instruction Set Computers (CISC)

complicated instruction set different instruction formats and lengths many different addressing modes e.g. VAX or PDP-11 from DEC e.g. Intel x86 family

Reduced Instruction Set Computer (RISC)

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RISC Machines

RISC system

instruction

standard, fixed instruction format single-cycle execution of most instructions memory access is available only for load and store instruction other instructions are register-to-register operations a small number of machine instructions, and instruction format

a large number of general-purpose registers a small number of addressing modes Three RISC machines

SPARC family PowerPC family Cray T3E