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Floorplanning: An Optimal Floorplan, in Terms of Area

This document discusses floorplanning techniques for integrated circuit design. It begins by defining the inputs and objectives of floorplanning such as a set of blocks, pin locations, and netlist. It then discusses terminology used in floorplanning like rectangular dissection and slicing trees. Different representations of floorplans are described including Polish notation and normalized Polish expressions. Neighborhood structures and types of moves in simulated annealing are defined. The document outlines the cost function, area and wiring length computations, and annealing schedule for a floorplanning algorithm. Finally, it briefly discusses using mathematical programming formulations for floorplanning.

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Santhi Sri
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0% found this document useful (0 votes)
20 views

Floorplanning: An Optimal Floorplan, in Terms of Area

This document discusses floorplanning techniques for integrated circuit design. It begins by defining the inputs and objectives of floorplanning such as a set of blocks, pin locations, and netlist. It then discusses terminology used in floorplanning like rectangular dissection and slicing trees. Different representations of floorplans are described including Polish notation and normalized Polish expressions. Neighborhood structures and types of moves in simulated annealing are defined. The document outlines the cost function, area and wiring length computations, and annealing schedule for a floorplanning algorithm. Finally, it briefly discusses using mathematical programming formulations for floorplanning.

Uploaded by

Santhi Sri
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 27

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Floorplanning
Inputs to the oorplanning problem:

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A set of blocks, xed or exible. Pin locations of xed blocks. A netlist.

Objectives: Minimize area, reduce wirelength for (critical) nets, maximize routability, determine shapes of exible blocks
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An optimal floorplan, in terms of area

A nonoptimal floorplan
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Floorplan Design

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x Modules: Area: A=xy

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3 1 5 e 2

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Aspect ratio: r <= y/x <= s

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Rotation: Module connectivity

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Floorplanning: Terminology
Rectangular dissection: Subdivision of a given rectangle by a nite # of horizontal and vertical line segments into a nite # of non-overlapping rectangles.

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1 2

4 6

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H
2 1 H
V

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H
3 2
V

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V 6 7 4 5

Skewed slicing tree: One in which no node and its right child are the same.
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1 V
6 7 V

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5 7
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Slicing tree: A binary tree, where each internal node represents a vertical cut line or horizontal cut line, and each leaf a basic rectangle.

Slicing structure: a rectangular dissection that can be obtained by repetitively subdividing rectangles horizontally or vertically.

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Nonslicing floorplan

Slicing floorplan

A slicing tree (skewed) Another slicing tree (nonskewed)


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Floorplan Design by Simulated Annealing


Related work

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Wong & Liu, A new algorithm for oorplan design, DAC86. Consider slicing oorplans.

Wong & Liu, Floorplan design for rectangular and L-shaped modules, ICCAD87. Also consider L-shaped modules.

Ingredients: solution space, neighborhood structure, cost function, annealing schedule?

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Wong, Leong, Liu, Simulated Annealing for VLSI Design, pp. 3171, Kluwer academic Publishers, 1988.

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Solution Representation
An expression E = e1 e2 . . . e2n1 , where ei {1, 2, . . . , n, H, V }, 1 i 2n 1, is a Polish expression of length 2n 1 i 1. every operand j , 1 j n, appears exactly once in E ; 2. (the balloting property) for every subexpression Ei = e1 . . . ei, 1 i 2n 1, #operands > #operators.

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1 6 H 3 5 V 2 H V 7 4 H V # of operands = 4 ....... = 7 # of operators = 2 ....... = 5

Polish expression Postorder traversal. ijH : rectangle i on bottom of j ; ijV : rectangle i on the left of j .

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4
H

6 1 2 3
1

2 7 5

6 E = 16H2V75VH34HV

E = 16+2*75*+34+* Postorder traversal of a tree!


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Solution Representation (contd)

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V
1
H 2 3

3 1 2

V
4 1

nonskewed!
Nonskewed cases

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....... HH ........

Question: How to eliminate ambiguous representation?


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H H

E = 123H4VV

or

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E = 123HV4V

skewed!
V V

....... VV ........

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Normalized Polish Expression


A Polish expression E = e1 e2 . . . e2n1 is called normalized i E has no consecutive operators of the same type (H or V ).

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Given a normalized Polish expression, we can construct a unique rectangular slicing structure.

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E = 16H2V75VH34HV
A normalized Polish expression

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Neighborhood Structure
Chain: HV HV H . . . or V HV HV . . .

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1 6 H 3 5 V 2 H V 7 4 H V

3 types of moves:

M 2 (Chain Invert): Complement some chain (V = H, H = V ). M 3 (Operator/Operand Swap): Swap two adjacent operand and operator.

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M 1 (Operand Swap): Swap two adjacent operands.

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Adjacent: 1 and 6 are adjacent operands; 2 and 7 are adjacent operands; 5 and V are adjacent operand and operator.

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Eects of Perturbation

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3 2 M2 1

4 3 1 2

M1

M 1 and M 2 moves are OK.

Check M 3 moves: Assume that the M3 move swaps the operand ei with the operator ei+1 , 1 i k 1. Then, the swap will not violate the balloting property i 2Ni+1 < i.
Nk : # of operators in the Polish expression E = e1 e2 . . . ek , 1 k 2n 1.

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Check the M 3 moves! Reject illegal M 3 moves.

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Question: The balloting property holds during the moves?

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12V4H3V

12V3H4V

or

12H3H4V

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2 M3 1

4 3

12H34HV

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Cost Function
= A + W .
A: area of the smallest rectangle

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W : overall wiring length

: user-specied parameter
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cij : # of connections between blocks i and j .

dij : center-to-center distance between basic rectangles i and j .

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W =

ij cij dij .

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M3

A: 12H34HV

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Cost Evaluation: Shape Curves


Shape curves correspond to dierent kinds of constraints where the shaded areas are feasible regions.

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wi hi hi wi

y = six

hi

wi

xi >= a, yi >= b

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Bounding area

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y

y = six

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y = six
y

u t n
y = ri x
x

hi

W
corner points

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feasible region

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1 y = six y = r ix y = r x

y = ri x

hi

1 x y=s
i

wi

wi hi

xi >= a, yi >= b or xi >= b, yi >= a

xi >= a, yi >= b xi yi >= A

xi >= a, yi >= b, xi yi >= A or xi >= b, yi >= a, xi yi >= A

(a) rigid, fixed orientation

(b) rigid, free (c) flexible, fixed (d) flexible, free orientation orientation orientation
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Area Computation

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{ (5,5) (9,4) }

2
H
{ (3,5) (6,,4) }

{ (2,5) (3,4) } H

2 3

2 1

{ (6,2) (3,3) }

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1

O
5

2
3

4 { (1,2) (2,1) } { (2,2) }

{ (1,3) (3,1) } { (2,3) (3,2) }

u1 v

u2

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u1 v

u2

u2 w

u1+u2

2
3

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V

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v+w
u1

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max{u1, u2}

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V
H
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{ (2,3) (3,2) } { (2,2) }

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V { (3,2) }

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max{v, w}

Wiring cost?
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Incremental Computation of Cost Function


Each move leads to only a minor modication of the Polish expression. At most two paths of the slicing tree need to be updated for each move.
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V

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W
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M1

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E = 12H34V56VHV

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H
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4
5

V 6

E = 12H35V46VHV

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Incremental Computation of Cost Function

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(contd)
H

H
V

O
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M2
1

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2

2
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V
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H

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V
1

E = 12H34V56VHV

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V
H

5
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E = 12H34V56HVH

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H
V 6

E = 12H34V56VHV

E = 123H4V56VHV
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Annealing Schedule
Initial solution: 12V 3V . . . nV .

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R
Ti = riT0 , i # of accepted moves < 5%, run out of time.

= 1, 2, 3, . . .; r = 0.85.

At each temperature, try kn moves (k = 510). Terminate the annealing process if temperature is low enough, or

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Algorithm: Simulated Annealing Floorplanning(P, , r, k) 1 begin 2 E 12V 3V 4V . . . nV ; /* initial solution */ 3 Best E ; T0 ln(avg ; M M T uphill 0; N = kn; P) 4 repeat 5 M T uphill reject 0; 6 repeat 7 SelectMove(M ); 8 Case M of 9 M1 : Select two adjacent operands ei and ej ; N E Swap(E, ei , ej ); 10 M2 : Select a nonzero length chain C ; N E Complement(E, C ); 11 M3 : done F ALSE ; 12 while not (done) do 13 Select two adjacent operand ei and operator ei+1 ; 14 if (ei1 = ei+1 ) and (2Ni+1 < i) then done T RU E ; 15 N E Swap(E, ei , ei+1 ); 16 M T M T + 1; cost cost(N E ) cost(E ); cost 17 if (cost 0) or (Random < e T ) 18 then 19 if (cost > 0) then uphill uphill + 1; 20 E N E; 21 if cost(E ) < cost(best) then best E ; 22 else reject reject + 1; 23 until (uphill > N ) or (M T > 2N ); 24 T = rT ; /* reduce temperature */ 25 until ( reject > 0.95) or (T < ) or OutOf T ime; MT 26 end

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Floorplanning by Mathematical Programming


Sutanthavibul, Shragowitz, and Rosen, An analytical approach to oorplan design and optimization, 27th DAC, 1990. Notation:

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wi, hi: width and height of module Mi.

(xi, yi): coordinate of the lower left corner of module Mi. ai wi/hi bi: aspect ratio wi/hi of module Mi. (Note: We dened aspect ratio as hi/wi before.)

Linear constraints? Objective function?

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Goal: Find a mixed integer linear programming (ILP) formulation for the oorplan design.

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wi hi

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Mi

Area = hi * wi Aspect ratio = wi / hi

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(xi, yi)

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Nonoverlap Constraints
Two modules Mi and Mj are nonoverlap, if at least one of the following linear constraints is satised (cases encoded by pij and qij ): pij qij Mi to the left of Mj : xi + w i xj 0 0 Mi below Mj : yi + h i y j 0 1 Mi to the right of Mj : xi wj xj 1 0 Mi above Mj : yi h j yj 1 1

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hi

wi

wj hj

wi

(xj, yj) (xi, yi) xi + wi <= xj

(xj, yj) (xi, yi) xi + wi > xj


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xi + w i yi + h i xi w j yi h j

xj + W (pij + qij ) yj + H (1 + pij qij ) xj W (1 pij + qij ) yj H (2 pij qij )

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Introduce two 0, 1 variables pij and qij to denote that one of the above inequalities is enforced; e.g., pij = 0, qij = 1 yi + hi yj is satised.

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Let W, H be upper bounds on the oorplan width and height, respectively.

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Cost Function & Constraints


Minimize Area = xy , nonlinear! (x, y : width and height of the resulting oorplan) How to x?

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Fix the width W and minimize the height y !

1. no two modules overlap (i, j : 1 i < j n); 2. each module is enclosed within a rectangle of width W and height H (xi + wi W, yi + hi H, 1 i n); 4. pij , qij {0, 1}. wi, hi are known.

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3. xi 0, yi 0, 1 i n;

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Four types of constraints:

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Mixed ILP for Floorplanning


Mixed ILP for the oorplanning problem with rigid, xed modules. min y

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subject to

Size of the mixed ILP: for n modules,

# continuous variables: O(n); # integer variables: O(n2 ); # linear constraints: O(n2 ). Unacceptably huge program for a large n! (How to cope with it?) Popular LP software: LINDO, lp solve, etc. 20

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xi + wi W, yi + hi y, xi + wi xj + W (pij + qij ), yi + hi yj + H (1 + pij qij ), xi wj xj W (1 pij + qij ), yi hj yj H (2 pij qij ), xi , y i 0 , pij , qij {0, 1},

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1in 1in 1i<jn 1i<jn 1i<jn 1i<jn 1in 1i<jn

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(1) (2) (3) (4) (5) (6) (7) (8)

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Mixed ILP for Floorplanning (contd)


Mixed ILP for the oorplanning problem: rigid, freely oriented modules. min y

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For each module i with free orientation, associate a 0-1 variable ri : ri = 0: 0 rotation for module i. ri = 1: 90 rotation for module i. M = max{W, H }. 21

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subject to xi + ri hi + (1 ri )wi W, yi + ri wi + (1 ri )hi y, xi + ri hi + (1 ri )wi xj + M (pij + qij ), yi + ri wi (1 ri )hi yj + M (1 + pij qij ), xi rj hj + (1 rj )wj xj M (1 pij + qij ), yi rj wj (1 rj )hj yj M (2 pij qij ), xi , yi 0, pij , qij {0, 1},

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1in 1in 1i<jn 1i<jn 1i<jn 1i<jn 1in 1i<jn

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(9) (10) (11) (12) (13) (14) (15) (16)

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Flexible Modules
Assumptions: wi , hi are unknown; area lower bound: Ai . Module size constraints: wi hi Ai ; ai Hence, wmin =
wi hi

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bi .
Ai , bi

Ai ai , wmax =

Ai bi , hmin =

hmax =

wi hi Ai nonlinear! How to x?

Can apply a rst-order approximation of the equation: a line passing through (wmin , hmax ) and (wmax , hmin ).

Substitute i wi + ci for hi to form linear constraints (xi , yi , wi are unknown; i , j , ci , cj can be computed as above).

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j . w

h i = i w i + c i hmax hmin i = wmin wmax ci = hmax i wmin

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/ y = mx + c / / slope / / c = y0 mx0 /

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h Ai = wi * hi

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h max

hi =

i wi

+ ci

h min

wmin

wmax

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Reducing the Size of the Mixed ILP


Time complexity of a mixed ILP: exponential! Recall the large size of the mixed ILP: # variables, # constraints: O(n2 ). How to x it?

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How to select next subgroup of modules? linear ordering based on connectivity.

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How to minimize the # of required variables?

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Questions:

Key: Solve a partial problem at each step (successive augmentation)

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Next group of modules

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Partial floorplan

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Reducing the Size of the Mixed ILP (contd)


Size of each successive mixed ILP depends on (1) # of modules in the next group; (2) size of the partially constructed oorplan.

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(a) C3 C2 C1 (c)

Keys to deal with (2)

Minimize the problem size of the partial oorplan.

Replace the already placed modules by a set of covering rectangles.

Dead space

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Horizontal cut edges

(d)

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(b)

# rectangles is usually much smaller than # placed modules.

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