Include Problem Statement
Include Problem Statement
Problem 2
library ieee; use ieee.std_logic_1164.all; entity asg2 is port(a,b,c : in std_logic; x1,x2,x3,x4,x5 : out std_logic); end asg2; architecture arch of asg2 is signal z,u: std_logic; begin x1 <= (not a and b) or (a and b); x2 <= a or (b and c); x3 <= (a and b) or (b and c); u <= b or c;
z <= not u; x4 <= (a and b) or z; x5 <= (a and b and c) or (not (a and b and c)); end;
Problem 3
library ieee; use ieee.std_logic_1164.all;
Problem 4
library ieee; use ieee.std_logic_1164.all;
entity asg4 is port (A,B,Cin : in std_logic; S, Cout : out std_logic); end asg4;
architecture arch of asg4 is signal w,x,y,z : std_logic; begin w <= b xor Cin; S <= a xor w; x <= b and Cin; y <= a and b; z <= a and Cin; Cout <= x or y or z; end;