Inverter Layout Alternatives
Inverter Layout Alternatives
Layout Examples
CMPE 413
Layout Examples
CMPE 413
XNOR
"Stacked layout" (on right): signals applied to multiple n- and p-transistors. Works well for cascaded gates.
Layout Examples
CMPE 413
Complex Logic Gates Line of diffusion rule Transistors form a line of diffusion intersected by poly. Diffusion will be unbroken if identically labeled Euler paths can be found for the p and n trees: C B A C D I3 A D I1 I2 B For example, A-B-C-D works here (see previous slide). Let vertices represent source/drain connections. Let edges represent transistors. Z
VDD Z D I3 I1 GND C
B I2 A Z
3
Layout Examples
CMPE 413
Layout Examples
CMPE 413
Layout Examples
CMPE 413
Layout Examples
CMPE 413