Scribd
Upload
46 views

Syllabus Layout For Esd

This course focuses on layout techniques for electrostatic discharge (ESD) protection devices used in integrated circuits. The course covers device compositions, parasitic effects, isolation schemes, and whole chip ESD protection methodologies. It aims to provide a basic understanding of ESD protection and the layout of devices like diodes, resistors, and MOS transistors used in ESD protection schemes.

Uploaded by

smusala7970
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
46 views

Syllabus Layout For Esd

This course focuses on layout techniques for electrostatic discharge (ESD) protection devices used in integrated circuits. The course covers device compositions, parasitic effects, isolation schemes, and whole chip ESD protection methodologies. It aims to provide a basic understanding of ESD protection and the layout of devices like diodes, resistors, and MOS transistors used in ESD protection schemes.

Uploaded by

smusala7970
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Layout for ESD

This course focuses on the layout of devices used in ESD protection schemes for ICs. Content includes device compositions, parasitic effects of ESD structures, isolation schemes, and whole chip ESD protection methodologies. COURSE CODE: ESDLT01 COURSE PRE-REQUISITE: None LEARNING OUTCOMES A basic understanding of ESD Protection methodologies Understanding the parasitic elements introduced by ESD structures Understanding the layout of ESD protection devices SYLLABUS CONTENT ESD Defined o Introduction to ESD o ESD protection schemes o ESD related failures CMOS Technology Review Diode ESD protection device Resistor ESD protection device MOS ESD protection device Ground/Power Strategies Design Rules specific to ESD o Electromigration issues (i.e. spacings, thickness, uniform current densities, etc.) RF/Mixed Signal ESD Protection Schemes o Parasitic effects of ESD protection structures o Noise Isolation Whole Chip ESD Protection Schemes o Input ESD Protection Schemes o Output ESD Protection Schemes o Power Clamps o Multiple domains COURSE DELIVERY 2-day lecture MORE INFORMATION http://www.icmaskdesign.com

IC Mask Design Ltd.

You might also like