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Risc Vs Cisc

This document provides an overview of CISC and RISC architecture. CISC uses complex instructions that take multiple clock cycles to execute and can directly reference memory. It has few general purpose registers. RISC uses simpler instructions that are executed within one clock cycle. It incorporates many general purpose registers and only load and store instructions can directly reference memory. Pipelining allows RISC processors to process multiple instructions simultaneously for improved efficiency.

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309 views9 pages

Risc Vs Cisc

This document provides an overview of CISC and RISC architecture. CISC uses complex instructions that take multiple clock cycles to execute and can directly reference memory. It has few general purpose registers. RISC uses simpler instructions that are executed within one clock cycle. It incorporates many general purpose registers and only load and store instructions can directly reference memory. Pipelining allows RISC processors to process multiple instructions simultaneously for improved efficiency.

Uploaded by

dlawand8241
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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RISC / CISC Architecture

Overview
CISC Architecture RISC Architecture
Pipelining

RISC vs CISC

What is CISC
Complex Instruction Set Computer High level Instruction Set Executes several low level operations Ex: load, arithmetic operation, memory store

Features of CISC
Instructions can operate directly on memory Small number of general purpose registers Instructions take multiple clocks to execute Few lines of code per operation

What is RISC?
Reduced Instruction Set Computer RISC is a CPU design that recognizes only a limited number of instructions Simple instructions Instructions are executed quickly

Features of RISC

Reduced instruction set Executes a series of simple instruction instead of a complex instruction Instructions are executed within one clock cycle Incorporates a large number of general registers for arithmetic operations to avoid storing variables on a stack in memory Only the load and store instructions operate directly onto memory Pipelining = speed

Pipelining
Assembly Line Technique to process multiple instructions at the same time Allows instructions to be executed efficiently

Stages of Pipelining
Fetch instructions from memory Decode the instruction Execute the instruction or calculate an address Access an operand in data memory Write the result into a register

CISC vs RISC
CISC RISC Complex instructions require multiple cycles Many instructions can reference memory Instructions are executed one at a time Few general registers Reduced instructions take 1 cycle

Only Load and Store instructions can reference memory Uses pipelining to execute instructions Many general registers

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