Phase Locked Loop Circuits

Reading:

General PLL Description: T. H. Lee, Chap. 15. Gray and Meyer, 10.4 Clock generation: B. Razavi, Design of Analog CMOS Integrated Circuits, Chap. 15, McGraw-Hill, 2001.

1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies must exactly track. out (t ) = in (t ) + const. out (t ) = in (t ) The PLL output can be taken from either Vcont, the filtered (almost DC) VCO control voltage, or from the output of the VCO depending on the application. The former provides a baseband output that tracks the phase variation at the input. The VCO output can be used as a local oscillator or to generate a clock signal for a digital system. Either phase or frequency can be used as the input or output variables.
Vcont in(t) in(t) out(t) out(t) VCO

Phase detector

ve(t)

Loop filter

Of course, phase and frequency are interrelated by: d (t ) = dt (t ) = (0) + (t ' )dt '
0 t

Applications: There are many applications for the PLL, but we will study: a. Clock generation b. Frequency synthesizer c. Clock recovery in a serial data link

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You should note that there will be different design criteria for each case, but you can still use the same basic loop topology and analysis methods. 2. Phase detector: compares the phase at each input and generates an error signal, ve(t), proportional to the phase difference between the two inputs. KD is the gain of the phase detector (V/rad). ve (t ) = K D [out (t ) in (t )] As one familiar circuit example, an analog multiplier or mixer can be used as a phase detector. Recall that the mixer takes the product of two inputs. ve(t) = A(t)B(t). If, A(t) = A cos(0t + A) B(t) = B cos(0t + B) Then, A(t)B(t) = (AB/2)[ cos(20t + A + B) + cos(A - B)] Since the two inputs are at the same frequency when the loop is locked, we have one output at twice the input frequency and an output proportional to the cosine of the phase difference. The doubled frequency component must be removed by the lowpass loop filter. Any phase difference then shows up as the control voltage to the VCO, a DC or slowly varying AC signal after filtering. The averaged transfer characteristic of such a phase detector is shown below. Note that in many implementations, the characteristic may be shifted up in voltage (single supply/single ended).
KD/2 Ve /2

- KD/2

If the phase difference is /2, then the average or integrated output from the XOR-type phase detector will be zero (or VDD/2 for single supply, digital XOR). The slope of the characteristic in either case is KD. 3. VCO. In PLL applications, the VCO is treated as a linear, time-invariant system. Excess phase of the VCO is the system output.

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out = K O Vcont dt '

The VCO oscillates at an angular frequency, out. Its frequency is set to a nominal 0 when the control voltage is zero. Frequency is assumed to be linearly proportional to the control voltage with a gain coefficient KO or KVCO (rad/s/v). out = 0 + KO Vcont Thus, to obtain an arbitrary output frequency (within the VCO tuning range, of course), a finite Vcont is required. Lets define out in = .

(Figure from B. Razavi, Ch. 15, op. cit.) In the figure above, the two inputs to the phase detector are depicted as square waves. The XOR function produces an output pulse whenever there is a phase misalignment. Suppose that an output frequency 1 is needed. From the upper right figure, we see that a control voltage V1 will be necessary to produce this output frequency. The phase detector can produce this V1 only by maintaining a phase offset 0 at its input. In order to minimize the required phase offset or error, the PLL loop gain, KD KO, should be maximized, since

0 =

V1 1 0 = K D K D KO

Thus, a high loop gain is beneficial for reducing phase errors. 4. PLL dynamic response: To see how the PLL works, suppose that we introduce a phase step at the input at t = t1.

in = 1t +0 + 1u (t t1 )

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(Figure from B. Razavi, Ch. 15, op. cit.) Since we have a step in phase, it is clear that the initial and final frequencies must be identical: 1. But, a temporary change in frequency is necessary to shift the phase by 1. The area under out gives the additional phase because Vcont is proportional to frequency.

1 = out dt = K OVcont (t )dt

t1 t1

After settling, all parameters are as before since the initial and final frequencies are the same. This shows that Vcont(t) [shown as VLPF (t) in the figure above] can be used to monitor the dynamic phase response of the PLL. Now, lets investigate the behavior during a frequency step:

2 = 1 +
The frequency step will cause the phase difference to grow with time since a frequency step is a phase ramp. This in turn causes the control voltage, Vcont, to increase, moving the VCO frequency up to catch up with the input reference signal. In this case, we have a permanent change in out since a higher Vcont is required to sustain a higher out.

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(Figure from B. Razavi, Ch. 15, op. cit.) If the frequency step is too large, the PLL will lose lock.

5. Lock Range. Range of input signal frequencies over which the loop remains locked once it has captured the input signal. This can be limited either by the phase detector or the VCO frequency range. a. If limited by phase detector:
KD/2 Ve /2

- KD/2

0 < < is the active range where lock can be maintained. For the phase detector type shown (Gilbert multiplier or mixer), the voltage vs. phase slope reverses outside this range. Thus the frequency would change in the opposite direction to that required to maintain the locked condition.

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Ve-max = KD /2 When the phase detector output voltage is applied through the loop filter to the VCO, out max = KV /2 = L (lock range) where KV = KO KD, the product of the phase detector and VCO gains. This is the frequency range around the free running frequency that the loop can track. Doesnt depend on the loop filter Does depend on DC loop gain b. The lock range could also be limited by the tuning range of the VCO. Oscillator tuning range is limited by capacitance ratios or current ratios and is finite. In many cases, the VCO can set the maximum lock range. 6. Capture range: Range of input frequencies around the VCO center frequency onto which the loop will lock when starting from an unlocked condition. Sometimes a frequency detector is added to the phase detector to assist in initial acquisition of lock. You will see later that the loop filter bandwidth has an effect on the capture range. 7. Approach: We will discuss the details of phase detectors and loop filters as we proceed. But, at this point, we will treat the PLL as a linear feedback system. We assume that it is already locked to the reference signal, and examine how the output varies with the loop transfer function and input. A frequency domain approach will be used, specifically describing transfer functions in the s-domain. Ve(s)/ = KD out(s)/Vcont(s) = KO /s Note that the VCO performs an integration of the control voltage and thus provides a factor of 1/s in the loop transfer function. Because of this, a PLL is always at least a first order feedback system.

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PLL is a feedback system

IN(s)

(s)
KFWD(s)

OUT(s)

KFB(s)

Loop Gain: Transfer Function:

T ( s ) = K FWD ( s ) K FB ( s )

(s) K OUT ( s ) = H ( s ) = FWD 1 + T (s) IN ( s)

The Loop gain can be described as a polynomial:

T ( s) =

K ' ( s + a )( s + b) s n ( s + )( s + )

ORDER = the order of the polynomial in the denominator TYPE = n (the exponent of the s factor in the denominator) PHASE ERROR =

( s) =

IN ( s) 1 + T (s)

STEADY STATE ERROR =

s 0 t (this is the Laplace Transform final value theorem)

SS = lim [ s ( s )] = lim (t )

SS error is a characteristic of feedback control systems. This is the error remaining in the loop at the phase detector output after all transients have died out. Once again, you can see that a large loop gain T(s) leads to a small phase error.

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Frequency and phase tracking loop:

First we will consider the PLL with feedback = 1; therefore, input and output frequencies are identical. The input and output phase should track one another, but there may be a fixed offset depending on the phase detector implementation.

r in ref

Phase Detector

Loop filter
F(s)

VCO
KO /s

out vco

KD

Transfer Function: H(s) = forward path gain / [1 + T(s)]. With feedback = 1, H(s) = T(s)/[1 + T(s)]

H( s ) =
Phase error function:

K D KO F( s ) / s out = in 1 + K D K O F ( s ) / s

s = in out =

sin s + K D KO F ( s)

For the frequency synthesis application, we want to have ideally perfect phase tracking for phase and frequency steps. When the synthesizer frequency is changed, it is a discontinuous step in modulus, and we want to have zero steady state phase error in this case.

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We will start from the open loop gain, T(s). T(s) = KDF(s)KO/s We know that the phase detector will be producing an output equal to or at twice the carrier frequency, thus some low pass filtering will be needed. Lets start with a simple RC lowpass network.

R C

This network has a cutoff (3 dB) frequency 1 = 1/RC. Thus, the filter transfer function is a simple lowpass,

F (s) =
Then, T(s) becomes second order, Type 1:

1 . 1 + s / 1

T (s) =

KO K D A KV = s 1 + s / 1 s (1 + s / 1 )

Bode Plot: Now look at the Bode plot of T(j).

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20 log |T(j)|

Crossover freq. 1 0 T(j) -90 PM

-180

If the loop filter frequency is lower than the crossover frequency, which you might want to do to attenuate the high frequency ripple from the phase detector, then the phase margin can become unacceptably small. And, if we increase the loop gain, KV = KDKO, to reduce the residual phase error, we get even smaller phase margin. Thus, we have a conflict between stability of the loop and minimizing the phase error. However, the loop can be made to work if 1 > crossover. But, then we may have insufficient filtering of the phase detector output. Before we fix this problem, lets look at the root locus and then the closed loop response of this PLL. Root Locus: Since there are no zeros, the root locus represents the roots of the denominator of the closed loop transfer function. Set 1 + T(s) = 0 and solve for s as a function of KV.

s=

4 KV 1 1 2 1

We see that as KV is increased, the roots approach one another then become complex conjugates.

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1
2

4 KV

1/2

We can have a very underdamped response when 1 << KV. Think about the inverse Laplace transform of the complex conjugate pole pair.

1 4 KV 1 e 1t / 2 sin 2 1

There is an exponentially decaying term determined by the real part of the roots that shows how long it takes the system to settle after a phase or frequency step and a ringing frequency dictated by the imaginary part of the pole pair. Again, when 1 << KV, we have a high ringing frequency and a long settling time, characteristic of a system that is not very useful. It is sometimes useful to define a natural frequency, n, and a damping factor, . This is standard control system terminology for a second order system. The key is to put the denominator of the closed loop transfer function, 1 + T(s), into a standard form: either
2 s 2 + 2 n s + n

or

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s2
2 n

s +1 .

Taking the first formula, 1 + T(s) can be written as:

s 2 + 1s + KV 1
so, we can associate n and with:

n = KV 1 =
1 1 2 KV

This form allows you to use standard equations and normalized plots to describe the frequency and transient response of the system. As we saw with the other ways of representing the frequency response of the system, a large KV, which we like for reducing phase error, leads to a small , which is bad for stability and settling time. For example, the transient response for a Type 1, second order lowpass system such as this is plotted in the next figure taken from Motorola App. Note AN-535. It is clear that damping factors less than 0.5 produce severe overshoot and ringing. In the frequency domain, the closed loop transfer function will also exhibit gain peaking when the system is underdamped. This is the same effect that we see with feedback amplifiers.

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So, it is clear that we need a better transfer function that gives us more flexibility in determining the bandwidth of the filter and the stability of the system. You cant obtain a narrow loop bandwidth without reducing the phase margin/damping factor. Add a zero to the loop filter transfer function to manipulate the root locus and improve stability.

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These parameters will have a strong effect on the loop dynamics which control overshoot and settling time. From the system design perspective, overshoot can be quite harmful, since it will cause the frequency to temporarily exceed the steady state value. Thus, the output of the synthesizer might land in an adjacent channel during part of the transient response. Settling time can also be critical since many TDM applications use different receive and transmit frequencies. The settling time determines how long you must wait until transmitting or receiving after a hop in frequency.

Ref. B. Razavi, RF Microelectronics, Prentice-Hall, 1998. Here you see the consequences of PLL settling time if the PLL is being used as a local oscillator for a receiver or transmitter.

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Adding a resistor to the lowpass loop filter contributes a zero to its transfer function.

R1 C

R2

F (s) =
where

1 + s / 2 1 + s / 1

1 =

1 ( R1 + R2 )C 1 R2C

2 =

Thus, the zero frequency is always higher than the pole frequency. Check out the Bode plot, root locus and transient response again.

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20 log |T(j)|

Crossover freq. 1 0 T(j) -90 PM -180

Note that the phase margin has increased. Now, small values of 1 can be used for narrower filter bandwidth, or higher KV values can be used for lower phase error without sacrificing phase margin. Note how phase margin now improves when the crossover frequency is increased due to higher gain. Root Locus: Calculate the closed loop transfer function for this PLL with the pole-zero loop filter.

o (1 + s 2 ) = 2 in 1 s 1 + s + +1 KV 1 KV 2

The denominator is of the form 1 + T(s). We can also extract n and from the closed loop transfer function since the denominator is in one of the standard forms.

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 n = KV 1 =
Then, solve for s; these are the poles.

1 1 1 n + 2 KV 2 2

s = n n 2 1

We see that n is the same as with the simple RC filter, but the damping factor has an added term. The first term is quite small in most cases, but the second term can be made large by increasing KV or reducing 2. We still have a type 1 system, but we have an added term that we can use to improve stability, the zero frequency. Note that the zero is in the forward path and therefore shows up in the closed loop transfer function. It will affect the frequency and transient response. FREQUENCY RESPONSE UCSB/ECE Department Prof S. Long 4/27/05 17

According to Gardner1, the loop bandwidth for this Type 1, second-order loop with a forward path zero is given by:

h = n 1 + 2 2 + (1 + 2 2 ) + 1

1/ 2

According to this, we have a bandwidth of about 2n for = 0.707. Refer to Fig. 2.3 from Gardner. This is a plot of the closed loop frequency response of a high gain second order PLL: 20 log |H(j)|. A high gain PLL is defined by KV/2 >> 1.

F. M. Gardner, Phaselock Techniques, Second ed., Wiley, 1979.

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From this plot, we can see how the 3 dB frequency and gain flatness varies with . Also, we see that the natural frequency must be significantly greater than the maximum frequency of phase variation for the reference (in) when < 1 in order to avoid gain peaking. This is a consequence of the zero added to the transfer function. For applications that require very small gain peaking (such as clock recovery), > 2 is often employed. PHASE ERROR There is no frequency error when the loop is locked Input frequency = output frequency But, it is possible to have a phase error for some input transient phase conditions. The phase error must remain bounded in order to keep the loop locked. To analyze in the frequency domain, we assume a sinusoidal phase variation at the input. PHASE ERROR =

( s) =

IN ( s) 1 + T (s)

STEADY STATE ERROR =

SS = lim[ s ( s)] = lim (t )

s 0 t

Fig. 2.4 from Gardners book illustrates how the phase error, expressed as
(s) = 20 log (out/in) dB

increases as the input frequency approaches the natural loop frequency for the case with = 0.707. For input phase variations well below the loop bandwidth, the loop tracks very well. This is because |T(jw)| is large at low frequency.

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TRANSIENT PHASE ERROR Inverse Laplace transform of (s) Now, lets look more closely at how the phase error is affected by the type of transient phase signal at the input of the Type I PLL. 1. Phase step. Because in(t) = u(t), in the frequency domain,

in ( s) =

The steady-state phase error can be calculated from (s) and ss above.

ss

s = lim =0 s 0 KV 1 + s / 2 1+ s s / 1 + 1 s

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Thus, there is only a transient phase error for a phase step. This is reasonable, because the control voltage must return to the same value after the phase step is completed. The frequency will be the same before and after the step. 2. Frequency step.

ss = lim

s2 = lim = s 0 1 + s / 2 KV K 1 + s / 2 s 0 + s K 1+ V V 1+ s / + s s / 1 1 1

There is a static error, but it can be made small by increasing KV. This is consistent with the idea that a shift in control voltage is needed to give a step in frequency. The phase error needed to generate this control voltage step varies inversely with the loop gain. 3. Frequency ramp. We could do the same exercise for a frequency ramp (Doppler shift). This gives an unlimited steady state error. So, a type I loop is not suitable for tracking a moving source. Summarizing:

Type I; second order:

F ( s )=

1 + s / 2 1 + s / 1

Input Phase step Freq. step Freq. ramp

in(s) /s /s2 A/s3

ss 0 /KV infinite

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For the frequency synthesis application, we want to have ideally perfect phase tracking for phase and frequency steps. When the synthesizer frequency is changed, it is a discontinuous step in modulus, and we want to have zero steady state phase error in this case. In the phase error analysis for the type 1 passive pole-zero lag filter, we found that there was a static phase error for a frequency step. To eliminate this phase error, we need a TYPE = 2 loop gain function. This requires an ideal integrator rather than a passive leadlag filter.

Type 2; second order:

F ( s )=

1 + s / 2 s / 1

Input Phase step Freq. step Freq. ramp

ref(s) /s /s2 A/s3

ss 0 0 kA

Placing an opamp RC integrator or charge pump in the loop will give a filter transfer function of the form:

F( s ) =

1 + s / 2 s / 1

where providing a pole at s = 0 and a zero at 2. Then, the loop gain T(s) will be that of a type 2 control system:

T( s ) =

K D K O ( 1 + s / 2 ) s 2 / 1

Details regarding the implementation of these filters will be presented later.

Now find the closed loop transfer function by inserting F(s). UCSB/ECE Department Prof S. Long 4/27/05 22

H( s ) =

out K D KO F( s ) / s = in 1 + K D K O F ( s ) / s
( 1 + s / 2 ) s2 s + +1 K D K O 1 2

H( s ) =

Thus, we can see that

n = K D K O 1 = n 2 2

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Ref. Motorola AN535 Here we see the phase and frequency step response for a type 2 PLL in terms of the key loop parameters. The settling time can be determined by setting an error tolerance around o(t) = 1. For example, if settling to 5% were the criteria and if = 1, the response first falls within the boundary of 0.95 or 1.05 for nt = 4.5. Then settling time t can be determined since natural frequency n will also be known.

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Root Locus:
Now, find the poles of 1 + T(s) = 0 Let KV = KOKD

s2 KV 1

+ 1=0

s = n n 2 1

Now examine the root locus. As the loop gain KV increases, both real and imaginary parts grow. The locus follows a circle centered around the zero. The poles become real again when = 1. This happens when KV = 422/1. We have the same geometric interpretation that was discussed in the FMD notes.

Increasing KV

(2)

- 2

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Bandwidth: The loop 3 dB bandwidth is important for noise considerations. It is determined by n and , so bandwidth must be determined in conjunction with the overshoot and settling time specifications. We find again that the formula is different for the case with a forward path zero as opposed to the feedback zero case that we discussed in the feedback lectures.

h = 3 dB = n 1 + 2 2 + ( 2 2 + 1 )2 + 1
3db = 2 n 3db = 2.5 n

1/ 2

for = 0.707 for = 1

Since the loop gain peaking and overshoot is greater when the zero is present, we also expect bandwidth to be higher as this shows. The effect of bandwidth on the synthesizer noise performance will be discussed later.

Loop Filter OpAmp

C R2

Vin
R1

Vbias

Vout

An op amp can be used to form a filter that includes a pole at s = 0 and a finite zero. For example, the circuit above can be analyzed using the virtual ground approximation to obtain F(s).

F( s ) =

Vout 1 + s R2 C = Vin s R1C

Vbias can be used to level shift between the phase detector and the VCO.

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Synthesizer PLL
We will now add the divider 1/N to the feedback path. This architecture is called an integer-N synthesizer.

osc r
1/M

Phase Detector +

Loop filter
F(s)

VCO
KO /s

ref

KD

out vco

1/N

Thus,

N 1 = out N and also, N = out ref

We can calculate the loop gain, T(s):

T (s) =

K D K O F ( s) Ns

We see that the loop gain is reduced by a factor of N. Also, in most applications, N is not constant, so KV = KDKO is not a constant varies with frequency according to the choice of N

Using the F(s) determined for the opamp pole-zero loop filter:

F (s) =

1 + s / 2 s / 1

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where 1 = 1/R1C and 2 = 1/R2C,

1 + T ( s) = 1 +

KV 1 + s / 2 =0 Ns s / 1

Ns 2 s 1 + T ( s) = + +1= 0 KV 1 2
We can now determine how the natural frequency and damping are affected by N:

n = =

KV 1 = N

KV R1CN KV C R1 N

n R = 2 2 2 2

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Phase Frequency Detector

The phase-frequency detector shown below is a widely used architecture in frequency synthesizers. As opposed to the XOR phase detector that we first considered, this one produces two outputs: QA and QB, or as is customary, UP and DOWN respectively.

Ref. J. Savoj and B. Razavi, High Speed CMOS for Optical Receivers, Kluwer Academic Publishing, 2001. (and many other books) This phase detector has a much larger phase range (4) of operation, and it will produce an output that drives the frequency in the right direction when it is out of lock. It also has zero offset when the phases are aligned and is insensitive to the duty cycle of the inputs since edge-triggered flip-flops are used.

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PFD characteristic. When the phases coincide, both outputs produce minimum width pulses. When there is a phase or frequency error, the width of the UP or DOWN pulses increases. When integrated by the loop filter, this causes the control voltage of the VCO to move toward the locked condition of equal frequency and phase. Because both outputs must be combined to obtain the desired output, the loop filter must be modified for differential inputs as shown below. F(s) is the same as that of the single ended version.

R2

DOWN UP

R1

_ +

R1 R2 C

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Charge Pump Loop Filter

An alternative loop filter implementation called the charge pump is widely used for many applications. It is very convenient to implement in CMOS.

The PFD output produces UP (QA) and DOWN (QB) pulses whose width is proportional to the phase error. Charge pump current sources I1 and I2 must produce exactly equal currents. They charge and discharge the capacitor, CP, in discrete steps. If there is a static phase error at the PFD input, the capacitor, C, will be charged indefinitely therefore, the DC gain is infinite: an ideal integrator. So, we expect to have zero static phase error. This is unlike the type I loop which gave = /KV steady state phase error. The CP PLL will detect small phase errors and correct them as long as the frequency of the phase error (jitter frequency) is within the loop 3 dB bandwidth. This phase comparison occurs on every cycle.

(from B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. To illustrate how the charge pump works and how it might be analyzed in a linearized model, refer to Fig. 15.32. Here we assume that I1 = I2 = IP and that a phase step occurs at t = 0.

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(from B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. First consider the time domain picture above. = 0 u(t) QA produces pulses that are of width

Tin = t . 2
IP charges Cp by

V =

IP I t = P 0 Tin CP C P 2

in every period. We can approximate this as a linear ramp with slope

slope =

IP 0 2C P

Thus, the output voltage from the charge pump can be described by

Vout ( t ) =

I P 0 t u( t ) 2C P

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The derivative of the step response is the impulse response, so we can determine the frequency domain transfer function.

h( t ) =

dVout I = P u( t ) 2C P dt

Take the Laplace transform to obtain the frequency domain transfer function.

H( s ) =

Vout ( s ) I 1 K PFD = P = 2C P s s

in(s) +

out(s)

KPFD/s

KVCO/s

PFD/CP/LPF

VCO

Here is the block diagram of the CP PLL. We see that the loop gain function T(s) has a factor of s2 in the denominator. Thus, it is a type II loop.

T( s ) =

K PFD KVCO s s

But, because of that, we have a big problem. The phase margin is always zero as shown by the Bode plot below.

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20 log |T(j)|

Crossover freq.

0 T(j) -90 PM = 0 -180

Therefore, we must add a zero to the loop filter transfer function to provide some phase lead to stabilize the PLL.

IP A PFD B QB IP CP QA UP DOWN RP VCO

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20 log |T(j)|

Crossover freq.
z

0 T(j) -90

-180
Now, we can see that an increase in the loop gain will improve phase margin. To determine T(s) for this case, we want to calculate Vout(s)/ again, adding the resistor to the charge pump filter. New filter:

Vout(s) I(s) RP CP

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The phase frequency detector (PFD) with single capacitor CP has

H( s ) =

Vout ( s ) I 1 K PFD = P = s 2C P s

To find the frequency response of the input current, we note that, I(s) = Vout(s)/Z(s) = Vout(s)/(1/sCP) where Z(s) is the complex impedance. So, the current source can be modeled as:

I( s ) I P = . 2
Now, lets use this to modify H(s) for the series RC loop filter. To do this, just replace the impedance 1/sCP with Z(s) = RP + 1/sCP.

Vout ( s ) I P 1 = + R P . 2 sC P
The loop gain T(s) is therefore

T( s ) =

out ( s ) I P 1 KVCO R = + P 2 sC P in s

I P KVCO (RP C P s + 1) 2C P s2

We see that a zero at = 1/RPCP has been added to the transfer function. This provides the necessary phase lead to achieve stability. Of course a frequency divider can be placed in the feedback path if the output frequency is to be multiplied by the PLL. Divide by N gives

out = Nin out = Nin

This added divider would be needed in a frequency synthesizer application or clock multiplier application.

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in(s) +

out(s)

KPFD/s

KVCO/s

1/N

T(s) is then modified by a factor of 1/N.

T( s ) =

I P KVCO (RP C P s + 1) 2NC P s2

Now, lets retain the factor of 1/N for completeness, and derive the closed loop transfer function. Define KV = IPKVCO/2CP and zero frequency wZ = 1/RPCP.

out ( s ) KV ( s / z + 1) / s 2 = in 1 + KV ( s / z + 1) / Ns 2
= N ( s / z + 1) N 2 s +1 s + z KV

Having put this in one of the standard forms, we can extract n and from the denominator.

n =

KV = N

I P KVCO 2 CP N
I P KVCO CP 2 N

n R = P 2 z 2

We can see now with RP = 0, = 0, therefore there is no phase margin and the system is unstable as expected. With added RP, the damping factor can be increased. Also note

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that stability will decrease with increasing N. Loop gain must be increased to compensate for this. The root locus of the modified charge pump PLL is shown below. It is the same as was obtained for the opamp loop filter.

(2) -1/RPCP

As loop gain is increased by increasing IPKVCO, the dual poles at s = 0 split and form a circular locus, rejoining the real axis at 1/2RPCP. The pole locations are found at

s = n n 2 1

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Closed Loop Frequency Response

The closed loop frequency response can be evaluated from H(j). In Fig. 2-3, Gardner has plotted the magnitude as a function of /n. Bandwidth: The loop 3 dB bandwidth is important for noise considerations. It is determined by n and , so bandwidth must be determined in conjunction with the overshoot and settling time specifications. We find again that the formula is different for the case with a forward path zero as opposed to the feedback zero case that we discussed in the feedback lectures.

h = 3dB = n 1 + 2 2 + (2 2 + 1) 2 + 1
3db = 2 n 3db = 2.5 n

1/ 2

for = 0.707 for = 1

Since the loop gain peaking and overshoot is greater when the zero is present, we also expect bandwidth to be higher as this shows. We see that the frequency response is a low pass to in. Thus, the phase noise of the reference source passes through the PLL and is filtered as shown in Fig. 2-3. Below the 3 dB frequency, we have little attenuation of input noise. Above, noise is reduced by 40 dB/decade. Also note that for < 2, there is gain peaking. Actually there is always some gain peaking for the Type II CP PLL or the opamp filter PLL because the zero frequency is always less than the pole frequency in the strongly damped case. For some applications, this is inconsequential. However, for clock and data recovery (CDR) use, the SONET specification is very strict: less than 0.1 dB of gain peaking is allowed. This is because in an optical fiber link, the signal may pass through several repeaters that include CDR units. Cascaded transfer functions with gain peaking leads to amplification of jitter (phase noise) close to the 3 dB frequency.

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Third-order CP PLL
There is still one residual problem that we have overlooked. The phase detector produces pulses of variable width that activate the switches to either charge or discharge the capacitor CP. Now that we have added the resistor, however, we find that the control voltage coming out of the charge pump will jump up or down before settling to its steady state value. This occurs because you cannot change the voltage across a capacitor instantaneously, so the initial voltage drop occurs across RP, which then charges CP exponentially. This jumpy control voltage frequency modulates the VCO at the reference frequency, creating reference spurs. This is not such a big problem if N = 1 because the jump will be at the same frequency as the VCO. But, at larger N values, it creates sidebands and jitter. So, we need to fix this by adding a second capacitor, C2, whose function is to filter out the jumpy response of the series RC network. The magnitude of the reference spur sidebands is reduced by a factor of REF/C2. Unfortunately, however, C2 adds a third

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pole of finite frequency that will reduce the stability of the PLL. A look at the Bode plot verifies this.

C 2 =

C P + C2 RP C P C 2

IP

IN
PFD

QA

UP DOWN VCO

QB

RP IP CP

C2

20 log |T(j)|

Crossover freq. z 0 T(j) -90 PM -180 C2

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The pole frequency is given by RP in parallel with the series combination of CP and C2. Thus, the pole is always higher in frequency than the zero. We can see that the added pole reduces the phase margin. In fact, now when the loop gain is increased, phase margin is reduced. So, we must be careful that the pole frequency added by C2 is much higher than the loop bandwidth.
C2 >> 10 C

More on this later..

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PLL Phase Noise

We have considered how the bandwidth of the loop affects things like settling time and capture range. But it also plays a role in the PLL noise behavior. For frequency synthesis, we are interested in low phase noise. There are at least 2 main sources: 1. reference noise usually small since we frequently use a crystal oscillator 2. VCO noise often high. We hope that the PLL will suppress most of the noise, at least close to the carrier.

The effect caused by each of these noise sources can be seen from the closed loop transfer functions. Phase noise filtering by the PLL: Reference Noise:

out Forward Path KV F ( s ) / s = = ref 1 + T (s) 1 + KV F ( s ) / N s

=
N (1 + s / 2 ) Ns 2 / KV + s / 2 + 1

This is a low pass transfer function. Its magnitude approaches N as s becomes small. Thus, reference phase noise is low pass filtered by the loop. Reference phase noise can be quite low when a crystal oscillator is used to generate the reference frequency. However, the phase noise gets multiplied by a factor of N for the integer N PLL.

out =N ref
This is a serious limitation for large N values. There are better architectures to be used when small step size and low phase noise are both required.

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VCO Noise:

out Forward Path 1 = = vco 1 + T ( s) 1 + KV F ( s ) / N s

= Ns 2 / KV Ns 2 / KV + s / 2 + 1

This is a high pass closed loop transfer function. It approaches a magnitude of 1 as s becomes large. While LC VCOs can have low phase noise, they generally have smaller tuning range. RC or ring oscillator VCOs can be built with very wide tuning range but poor phase noise. The PLL can be used to clean up the VCO phase noise within the loop bandwidth. VCO phase noise is unattenuated at offset frequencies beyond the loop bandwidth. Conclusions: 1. Reference input noise (reference source noise, data jitter, phase noise on FM input signal, etc.) sees a low-pass transfer function. It is passed through and multiplied by N. All we can do is try to avoid making it worse with our loop. A narrow bandwidth loop filter will help to suppress high frequency noise coming into the PLL from the reference port. 2. VCO jitter is suppressed by the PLL within the loop bandwidth. It has a high-pass transfer function. Thus, to suppress VCO noise, we want a large loop bandwidth.

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Reference Spurs.
The Integer N PLL has an inherent conflict between the frequency step size (increment) and the settling time/bandwidth. The phase detector produces pulses that are at the reference frequency, fR. These pulses are filtered by the loop lowpass filter, but not completely. Any residual reference frequency component on the VCO tuning voltage produces frequency modulation. Sidebands called reference spurs appear on both sides of the desired output spectral line spaced by fR. The natural frequency of the loop must be well below the reference frequency so that the reference frequency component is well attenuated by the loop filter.

n R / 10
Since the settling time and loop bandwidth are directly affected by n, we have conflicting requirements. Compromises must be made. One approach to further reducing reference sidebands is to create a third order loop by adding another pole to the loop filter.
R2

R1/2 C2 R1/2 C2

R1/2

_ +

C1

PD inputs

R1/2 R2 C1

Resistor R1 has been split in half and capacitor C2 added to produce a finite pole at

C 2 = 4 / R1C 2 .
This suppresses the reference spurs by a factor of R/C2 at the expense of stability.

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Reference sidebands (spurs)

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