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ECE 3110: Introduction To Digital Systems: XOR, Parity Circuits, Comparators

This document discusses combinational logic design practices involving XOR and XNOR gates, parity circuits, and comparators. It defines XOR and XNOR gates using their truth tables and logic equations. Parity circuits are described for odd and even parity using XOR gates in daisy chain and tree structures. Comparators are introduced for equality, magnitude, and iterative designs. MSI chips like the 74x85 are presented as 4-bit comparators. Applications of parity circuits for memory error checking and comparators in magnitude comparisons are also covered.

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46 views

ECE 3110: Introduction To Digital Systems: XOR, Parity Circuits, Comparators

This document discusses combinational logic design practices involving XOR and XNOR gates, parity circuits, and comparators. It defines XOR and XNOR gates using their truth tables and logic equations. Parity circuits are described for odd and even parity using XOR gates in daisy chain and tree structures. Comparators are introduced for equality, magnitude, and iterative designs. MSI chips like the 74x85 are presented as 4-bit comparators. Applications of parity circuits for memory error checking and comparators in magnitude comparisons are also covered.

Uploaded by

RajneeshKandimalla
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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ECE 3110: Introduction to Digital Systems

Chapter 6 Combinational Logic Design Practices

XOR, Parity Circuits, Comparators

Exclusive OR and Exclusive NOR Gates

XOR

X Y X 'Y X Y '
( X Y )' X Y X 'Y '

X F

XNOR :

Truth Table :
X 0 0 1 1 Y 0 1 0 1 XOR XNOR 0 1 1 0 1 0 0 1

XOR
X F

XOR
2

XOR and XNOR Symbols


Equivalent Symbols of XOR gate

Equivalent Symbols of XNOR gate

Any 2 signals (inputs or outputs) may be complemented without changing the resulting logic function
3

SSI XOR and XNOR


74x86 : 4 XOR gates
74x266: 4 XNOR gates with open collector or open drain output

XOR Application: Parity Circuit


Odd Parity Circuit : The output is 1 if odd number of inputs are 1 Even Parity Circuit : The output is 1 if even number of inputs are 1 Example : 4-bit Parity Circuit
I0 I1 I2 I3 EVEN ODD

I0
I1 I2 I3

EVEN
ODD

Daisy-Chain Structure Input : 1101

Tree structure

Odd Parity output : 1 Even Parity output : 0

MSI Parity Circuit : 74x280

Parity-Checking Application: memory

Comparators
Compares Two binary words and indicate if they are equal
A Comparator B A=B?

Magnitude Comparators :
A Comparator B A=B A>B A<B

Equality Comparators
1-bit comparator

4-bit comparator

EQ_L
9

Iterative Comparator

10

Multi-bit Iterative Comparator

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MSI Comparator : 74x85


4 bit comparator 3 outputs : A=B, A<B, A>B 3 Cascading inputs Functional Output equations : (A>B OUT)= (A>B)+(A=B).(A>B IN) (A<B OUT)= (A<B)+(A=B).(A<B IN) (A=B OUT)= (A=B).(A=B IN) Cascading inputs initial values : (A=B IN) =1 (A>B IN) =0 (A<B IN) =0
74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3
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8 bit Comparator
+5V
74x85 A<BIN A<BOUT A=BIN A=B OUT 74x85 A<BIN A<BOUT A=BIN A=B OUT A<B A=B

A>BIN A>BOUT
A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7

A>BIN A>BOUT
A0 B0 A1 B1 A2 B2 A3 B3

A>B

Least Significant bits

Most Significant bits

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8-bit Magnitude Comparator

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Other conditions

15

Next
Adders, subtractors, ALUs

Reading Wakerly CH-6.10-6.11

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