NOR Gate Beha - Modeling

The document describes a VHDL code for a NOR gate using behavioral modeling. It defines an entity with inputs l and m and output n. The architecture contains a process that sets the output n to the logical NOT of input l if m is 0, otherwise it sets n to 0 based on the NOR truth table. The process is sensitive to changes in the inputs l and m. It then provides a truth table and describes the architecture and output waveform.

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NOR Gate Beha - Modeling

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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R) NOR GATE VHDL CODE USING BEHAVIOURAL MODELING

library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------------entity nor_1 is Port ( l, m : in STD_LOGIC; n : out STD_LOGIC); end nor_1; ----------------------------------------------architecture Behavioral_nor of nor_1 is begin ----------------process(l, m) begin if(m='0') then n<= not l; else n<= '0'; end if; end process; ----------------end Behavioral_nor; TRUTH TABLE: -

*\\ l and m are the input port to the and gate. *\\ n is output port to the and gate.

*\\ architecture of nor_1 entity begins. *\\ process (sensitivity list). After this statement all statement will be *\\ if (condition is true) then output (n) equal to not of l.

*\\ otherwise output (n) equal to 0.

*\\ end the architecture.

OUTPUT WAVEFORM: -

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