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Design and Verification Engineer at Incise Infotech PVT LTD From Last 1.5 Year (July 2012-Present)

Rudresh Aravapalli is a design and verification engineer with over 1.5 years of experience. He has expertise in digital design and advanced verification techniques including AMBA AXI slave protocol, I2C Protocol, and developing tools using QuestaSim. He has worked on developing an AMBA AXI Slave Protocol as part of a team. He also has experience with Viterbi decoding algorithms and has worked as part of a team to develop an iterative decoder.

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Rudresh Aravapalli
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42 views

Design and Verification Engineer at Incise Infotech PVT LTD From Last 1.5 Year (July 2012-Present)

Rudresh Aravapalli is a design and verification engineer with over 1.5 years of experience. He has expertise in digital design and advanced verification techniques including AMBA AXI slave protocol, I2C Protocol, and developing tools using QuestaSim. He has worked on developing an AMBA AXI Slave Protocol as part of a team. He also has experience with Viterbi decoding algorithms and has worked as part of a team to develop an iterative decoder.

Uploaded by

Rudresh Aravapalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Rudresh Aravapalli Email : rudresh.aravapalli@yahoo.

com

Contact: 9871215161

PROFILE: Design and Verification engineer at ncise nfo!ech "vt #td from last 1.5 year $%uly 2&12' present(. SUMMARY:

Expertise in digital design and advanced verification techni !es "esign and #erification of AM$A A%I slave protocol& I'( Protocol) !ools and )ethodology *uesta +im ,V) "evelop.ent of AM$A A%I Slave Protocol) !eam )em-er .)/. is a registered trademar0 of .1) #imited and is an open standard2 on'chip interconnect specification for the connection and management of functional -loc0s in a +ystem'on'3hip $+o3(. t facilitates right'first'time development of multi' processor designs 4ith large num-ers of controllers and peripherals. Soft/are Platfor.0,ools5 *uesta +im Lang!age: Verilog2 +ystem Verilog2 ,V) Pro-ect: "evelop.ent of #iter1i decoder Role: !eam )em-er "etails: Viter-i algorithm is -eing 4idely used in many 4ireless and mo-ile communication systems for optimal decoding of 3onvolution codes. !he Viter-i alignment is a dynamic programming algorithm for finding the most li0ely se6uence of hidden states 7 called the Viter-i path 7 that results in a se6uence of o-served events2 especially in the conte8t of )ar0ov information sources and hidden )ar0ov models. .pplications using Viter-i decoding include digital modems and digital cellular telephone2 4here lo4 latency2 component cost and po4er consumption are must. Soft/are Platfor.0,ools5 *uesta+im Lang!age: Verilog2 +ystem Verilog $,V)(2 ,V). Pro-ect: Role: "etails:

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