Electronics and

Computer Systems Engineering

Altium Designer Guide









Tutorial part 2 PCB Design

This is Part 2 of a beginners guide to PCB design using Altium Designer and is geared towards the
following individuals:

POSSESS AMPLE THEORETICAL ELECTRONICS KNOWLEDGE
HAS LITTLE OR NO PCB DESIGN EXPERIENCE
HAS LITTLE OR NO ALTIUM DESIGNER EXPERIENCE




2

Creating the PCB
ONE OF THE REASONS WHY IT IS IMPORTANT TO DEFINE THE PCB FOOTPRINTS WHILE ENTERING IN THE SCHEMATIC IS TO
BE ABLE TO PROVIDE A GOOD ESTIMATE OF HOW MUCH BOARD AREA YOU WILL NEED.
GENERALLY SPEAKING THE FOLLOWING THINGS MAKE PRODUCTION MORE EXPENSIVE
LARGER AREA
MORE LAYERS
SMALLER HOLES
CLOSER TOLERANCES
CLOSER TRACES AND SPACING
THINNER OR THICKER PCB

OUR GOAL IS TO KEEP COST AS LOW AS POSSIBLE WHILE STILL BEING ABLE TO TRANSFER A SCHEMATIC TO A
FUNCTIONING PCB.
THERE ARE NO SPECIAL CHARACTERISTICS OF THIS DESIGN THAT REQUIRE ANY EXOTICS, AND WE CAN USE A 2 LAYER PCB
FOR LOW COST

FROM THE PROJECT TAB IN THE BOTTOM LEFT CORNER, CLICK THE FILES TAB AND
CLICK THE UPWARD FACING ARROWS UNTIL YOU CAN SEE
NEW FROM TEMPLATE
SELECT PCB BOARD WIZARD


3

YOU WILL GET A VERY FRIENDLY WIZARD SCREEN, CLICK NEXT TO CONTINUE

CHOOSE THE BOARD UNITS AS IMPERIAL
NOTE: YOU ARE NOT STUCK WITH THE CHOICE OF UNITS THAT YOU CHOOSE HERE. THE UNITS SPECIFIED ARE ONLY
USED FOR THE PCB WIZARD

4

THERE ARE MANY PREDEFINED TEMPLATES FOR EXOTIC DESIGNS OR STANDARD PCB COMPUTER INTERFACE FORMS,
SUCH AS AT BUS, PCI BUS, EUROCARD, AND MANY OTHERS.

CHOOSE CUSTOM (AT THE TOP)


LEAVE THE DEFAULT SETTINGS (RECTANGULAR, 5000 MILS X 4000 MILS )
THE DIMENSIONS OF THE BOARD WILL BE ON A GENERIC, INFORMATION LAYER (MECHANICAL LAYER) WHICH IS USED TO
GIVE INFORMATION TO THE BOARD HOUSE.

WE WANT TO HAVE A TWO LAYER BOARD. THIS IS TWO SIGNAL LAYERS (TOP OF BOARD, BOTTOM OF BOARD) AND ZERO
INTERNAL PLANE LAYERS, MAKE THIS CHANGE
5

DO YOU REMEMBER WHAT A POWER PLANE IS ? HOW DOES IT DIFFER FROM A SIGNAL LAYER? (HINT: YOU CAN HAVE
SIGNAL LAYERS INTERNAL OR EXTERNAL, AND YOU CAN HAVE POWER PLANES INTERNAL AND EXTERNAL)

MAKE SURE THE HOLE TYPE IS SET ON THRUHOLE VIAS ONLY
DO YOU REMEMBER WHAT A VIA IS ??


6

OUR BOARD CONTAINS MOSTLY SURFACE MOUNT COMPONENTS, SO CHECK THIS OPTION
CHOOSE THAT BOTH SIDES OF THE BOARD CAN CONTAIN COMPONENTS.
NOTE: THESE SETTINGS REALLY DONT MATTER. THEY EXIST FOR THE AUTOROUTER WHICH WE WILL NOT BE USING



CHANGE TRACK SIZE (10MILS) AND TRACE CLEARANCE (8 MILS)
WHAT IS THE METRIC LENGTH OF 8 MILS ????
CHANGE THE MINIMUM VIA HOLE SIZE TO 15 MILS, AND THE MIN. VIA WIDTH TO 30 MILS
NOTE: ALWAYS BE SURE YOUR SETTINGS CAN BE FABRICATED AT A REASONABLE PRICE BEFORE SETTING THESE VALUES


7

THE WIZARD IS NOW COMPLETE AND YOUR PCB IS CREATED BASED ON THE VALUES YOU HAVE GIVEN.

RIGHT CLICK ON THE PCB >
CLICK OPTIONS
CLICK BOARD OPTIONS

8

UNCHECK DISPLAY SHEET (THIS HAS A USE, BUT FOR NOW WE WANT TO REDUCE CLUTTER)
CHANGE THE MARKERS FROM LINES TO DOTS AND CLICK OK.
NOTE: THE SNAP GRID AND COMPONENT GRID ARE VERY IMPORTANT, WE WILL GET INTO THIS LATER THOUGH.


THE PCB HAS BEEN ADDED TO THE LIST OF DOCUMENTS, BUT HAS
NOT BEEN ADDED TO THE PROJECT (NOTICE IT IS LISTED AS A FREE
DOCUMENT)

CLICK AND DRAG THE PCB TO YOUR PROJECT
RIGHT CLICK ON THE PCB1.PCBDOC FILE AND SAVE THE FILE IN
YOUR PROJECT DIRECTORY.
SAVE THE FILE AS DEV BOARD


9

IF YOU GET THE FOLLOWING WARNING, JUST CLICK OK. IT IS TELLING YOU THERE MAY BE COMPATIBILITY ISSUES IF YOU
TRY TO OPEN THE PCB DOCUMENT IN AN OLDER VERSION OF ALTIUM.


IF YOU SELECT YOUR SCHEMATIC AGAIN, CLICK THE DESIGN BUTTON UP TOP AND THEN CLICK ON UPDATE PCB
DOCUMENT DEV BOARD.PCBDOC
THIS WILL BEGIN THE PROCESS TO TURN YOUR SCHEMATIC INTO A PCB

10

THIS WILL OPEN THE ECO (ENGINEERING CHANGE ORDER)
THIS IS ASKING WHICH CHANGES TO MAKE.
VALIDATE CHANGES WILL CHECK FOR ERRORS IN THE PROCESS
EXECUTE WILL ACTUALLY PERFORM THE CHANGE

CLICK VALIDATE AT THE BOTTOM. THIS MAY TAKE A WHILE DEPENDING ON THE COMPLEXITY OF THE PROJECT.
NOTICE THE GREEN CHECK BOXES TO THE RIGHT. THIS MEANS THAT EACH STEP WITH THE GREEN CHECK MARK CAN BE
PERFORMED SUCESSFULLY.
I HAVE DELIBERATELY REMOVED THE LIBRARY FOR THE USB CONNECTOR TO SHOW WHAT WILL HAPPEN IF THERE IS AN
ERROR FOR A STEP (RED X) ADDING THE LIBRARY WILL FIX THIS ERROR

11

BECAUSE THERE ARE USUALLY MANY DIFFERENT STEPS TO CREATING THE ECO, IT IS USUALLY HELPFUL TO CHECK THE
BOX THAT SAYS ONLY SHOW ERRORS AT THE BOTTOM.
YOU ARE IN GOOD SHAPE WHEN NO ERRORS OCCUR AND THIS LIST IS EMPTY

WHEN NO ERRORS APPEAR DURING THE VALIDATION STEP, YOU CAN CLICK THE EXECUTE CHANGES TO ACTUALLY
IMPORT THE SCHEMATIC TO THE PCB

YOU WILL SEE A SECOND ROW OF GREEN CHECK BOXES WHEN YOU EXECUTE THE CHANGES. AGAIN, CHECK FOR ERRORS
BY CHECKING THE ONLY SHOW ERRORS

12

NOTE: EVERY TIME YOU PERFORM AN ECO, THE RESULTS ARE SAVED IN A TEXT FILE IN YOUR PROJECT DIRECTORY

EXPORT THE NETLIST FOLLOWING THE MENU SEQUENCE BELOW (YOU MUST BE ON THE PCB DOCUMENT, NOT THE
SCHEMATIC DOCUMENT
THIS WILL EXPORT THE NETLIST TO YOUR PROJECT DIRECTORY

13

THE NETLIST CONTAINS INFORMATION SUCH AS PARTS, FOOTPRINT, AND VALUE (AS SHOWN BELOW)

IT ALSO CONTAINS CONNECTION INFORMATION AS SHOWN TO THE RIGHT

EACH NETLABEL (EITHER ASSIGNED BY YOU OR THE SOFTWARE, EVERY NET HAS A NETLABEL)
SHOWS WHICH COMPONENT AND PIN NUMBER CONNECTS TO THAT NODE

OBVIOUSLY A CONNECTION LIKE GND WILL HAVE MANY CONNECTIONS, AND NETLABELS
SUCH AS MISO MIGHT ONLY HAVE A FEW (3 IN THIS CASE)
14

NETLIST CONNECTIONS FOR NET MISO:
P3 PIN 9
P1 PIN 5
U1 PIN 16
A QUICK LOOK AT THE SCHEMATIC SHOWS THAT THIS NET IS PROPERLY CONNECTED



Creating the Netlist
FORTUNATELY, ALTIUM HANDLES THE NETLIST TRANSPARENTLY TO THE END USER, BUT IT IS IMPORTANT TO AT LEAST
BE FAMILIAR WITH THE TERM AND HOW THE SCHEMATIC IS TRANSFERRED TO THE PCB AND VICE VERSA

ANY CHANGES THAT ARE MADE MUST BE MADE TO THE NETLIST.

THE NETLIST IS THE LINK BETWEEN THE PCB AND THE SCHEMATIC. IT IS IMPORTANT THAT THE SCHEMATIC AND PCB
AGREE ON CONNECTIONS, NETS, FOOTPRINTS, ETC..
AFTER EXECUTING CHANGES. IF THERE ARE ERRORS OR NOT, WHATEVER THE SOFTWARE CAN IMPORT INTO THE PCB IT
WILL DO SO
NOTICE HOW THE SOFTWARE JUST SORT OF DUMPS ALL YOUR PARTS (PCB FOOTPRINTS) OFF TO THE SIDE OF THE
BOARD.
DOES ANYONE KNOW WHY THE SOFTWARE DOESNT PLACE THE PARTS ???

YOU MAY HAVE NOTICED THE WORDS ON THE RIGHT ON YOUR DESIGN. LEAVE IT WHERE IT IS AND DONT MESS WITH IT.
15

WE WILL GET TO THAT LATER WHAT IT DOES
THIS IS CALLED A SPECIAL STRING

NOTICE HOW ALL THE PARTS ARE PLACED INSIDE A COLORED RECTANGLE BOX CALLED MAIN. THIS IS CALLED A ROOM.
ROOMS ARE USED TO GROUP COMMON CIRCUIT TYPES. A ROOM IS CREATED FOR EACH SCHEMATIC PAGE WE HAVE
SINCE WE ONLY HAVE ONE PAGE, CALLED MAIN, THERE IS ONLY ONE ROOM

ROOMS ARE LIKE BORDERS FOR YOUR PARTS. AN ITEM INSIDE A ROOM CANNOT ESCAPE WITHOUT AN ERROR MESSAGE.
SINCE WE ONLY HAVE ONE ROOM, WE CAN DELETE THE ROOM WITHOUT AFFECTING OUR LAYOUT AT ALL.
CLICK ANYWHERE IN THE ROOM AND HIT THE DEL KEY
THE ROOM WILL DISAPPEAR AND THE COMPONENTS WILL REMAIN
NOTE: YOU CAN DISABLE THE USE OF ROOMS IN PROJECT OPTIONS

16

IF YOU HIT THE L KEY ON THE PCB PAGE, IT WILL BRING UP THE FOLLOWING DIALOG.
CHANGE THE OPTION UNDER MECHANICAL LAYERS THAT SAYS USED LAYERS ONLY


NOTICE THE DIFFERENT TABS AT THE BOTTOM OF THE SCREEN. THE SELECTED LAYER WILL LOOK DIFFERENT THAN THE
OTHERS (IN THIS CASE, TOP LAYER)
UNLIKE A SCHEMATIC, WHICH IS 2D, A PCB IS A 3D ENTITY WITH A WHOLE BUNCH OF LAYERS ON TOP OF EACH OTHER.
THESE LAYERS ARE ALL COMBINED TO FORM YOUR PCB.
NOTE: THESE LAYERS ARE ALL COLOR CODED!!!!

17

IF WE ZOOM IN, NOTICE THAT U2 (THE FT232 CHIP) HAS SEVERAL GREEN PADS, AND SEVERAL RED PADS.
THE RED PADS REPRESENT SOMETHING ON THE TOP LAYER. BUT WHY ARE SOME OF THE PADS GREEN ??




IF WE TYPE L AGAIN, IT WILL BRING UP THE
BOARD LAYER LISTS.
SINCE THE LAYERS ARE COLOR CODED, WE CAN
QUICKLY LOOK FOR THE GREEN ONE AND NOTICE
THAT THIS IS A DRC ERROR MARKER (DESIGN
RULE CHECK)
FOR SOME REASON ALTIUM HAS A PROBLEM
WITH OUR FT232 CHIP

CHECK (SELECT) THE BOXES FOR PAD HOLES AND
VIA HOLES

18

IF WE PUT THE MOUSE OVER ONE OF THE GREEN PADS, IT WILL TELL US INFORMATION ABOUT THE PAD, MOST
IMPORTANTLY IT WILL TELL US WHAT THE ERROR IS
FOR THESE PADS, THERE IS A CLEARANCE CONSTRAINT ERROR BETWEEN A PAD ON THE TOP LAYER, AND ANOTHER PAD
ON THE TOP LAYER
NOTE: IT IS UP TO YOU TO DECIDE IS THIS IS A REAL ERROR, OR AN IMPROPERLY SET RULE
IN THIS CASE IT IS AN INCORRECTLY SET RULE. THE PADS ON THIS FOOTPRINT ARE 8MIL APART, THE CLEARANCE IS SET TO
10MIL, HENCE THE ERROR.


LIKE THE SCHEMATIC, THERE ARE RULES WE NEED TO SET.
CLICK DESIGN > RULES (OR) RULES WIZARD TO CREATE/MODIFY RULES
NOTE: THE SOFTWARE ONLY CREATES ERRORS BASED ON YOUR RULES. IT IS UP TO YOU TO KNOW IF SOMETHING IS OK
OR NOT. IF YOU TELL THE SOFTWARE THAT 2 MIL TRACES ARE OK, THE SOFTWARE WILL ENFORCE THAT.

19

THE DRC EXPECTS A MINIMUM SPACING BETWEEN DIFFERENT NETS OF 8 MILS.

MAKE THE FOLLOWING RULE CHANGES (FROM TOP OF LIST DOWN):

MAX TRACE WIDTH= 200 MILS

MINIMUM VIA SIZE = 15 MILS, MIN VIA DIAMETER = 30 MILS
MAXIMUM VIA SIZE = 50 MILS, MAX VIA DIAMETER = 80 MILS
20

MINIMUM HOLE SIZE = 15 MILS, MAX HOLE SIZE = 200

21

TRY USING TRIAL AND ERROR AND CHANGE THE SETTING FOR MINIMUM CLEARANCE TO 7 MILS AND YOULL NOTICE THE
ERROR MARKERS GO AWAY.

NOTE: THERE ARE MANY BETTER WAYS OF DETERMINING THE ACTUAL SPACING, BUT WE WANT TO KEEP THINGS SIMPLE
FOR NOW


NOTICE THE SMALL LINES, THESE ARE COLLECTIVELY
REFERRED TO AS A RATSNEST.
IT IS A WAY OF TELLING YOU WHICH CONNECTIONS NEED
TO BE MADE STILL
EXAMPLE: YOU CAN SEE PIN 2 OF R12 NEEDS TO CONNECT
TO PIN 2 OF THE USB CONNECTOR

22

COMPONENTS ARE MOVED IN THE PCB THE SAME WAY THEY ARE MOVED IN THE SCHEMATIC.
NOTICE HOW THE RATSNEST CONNECTIONS REMAIN AND WILL DYNAMICALLY CHANGE BASED ON HOW A COMPONENT
IS ROTATED.


THERE IS USUALLY A TRADEOFF WHEN PLACING COMPONENTS. THIS USB CONNECTOR MIGHT BE EASIER TO ROUTE IF IT
IS IN THE MIDDLE OF THE BOARD, BUT WILL BE DIFFICULT FOR A USER TO USE A CONNECTOR IN THE MIDDLE OF THE
BOARD.
FOR THIS DESIGN, DO THE BEST YOU CAN TO MAKE IT EASIER TO ROUTE, FOR YOUR PROJECT, IT SHOULD MAKE PHYSICAL
SENSE TO AN END USER, EVEN IF IT MEANS HARDER ROUTING

EVERYONES PCB WILL BE DIFFERENT!!!

DO NOT TRY TO MAKE YOURS EXACTLY LIKE MINE OR ANYONE ELSES.
THIS DESIGN I WENT OUT OF MY WAY TO CREATE A MORE DENSE DESIGN FOR CLARITY AND TO RESIZE THE BOARD. FEEL
FREE TO USE THE ENTIRE BOARD AREA.

USUALLY, COMPONENTS THAT ARE CLOSE TOGETHER IN THE SCHEMATIC ARE PLACED CLOSE TOGETHER IN THE PCB.
NOTE: IF YOU HAVE TWO MONITORS, KEEP THE SCHEMATIC OPEN ON ONE SIDE, AND THE PCB ON THE OTHER SIDE. IF
YOU HAVE ONE MONITOR, JUST WRITE DOWN THE COMPONENTS
23


FOR THE USB CIRCUIT, WE WILL GROUP THE FOLLOWING COMPONENTS
C7- C11
R12 R16
U2
D9, D10

24

NEXT GROUP THE COMPONENTS AS THEY ARE ARRANGED
IN THE SCHEMATIC.

PRIORITIZE THE PLACEMENT BY ORGANIZING THE HIGH
SPEED OR CRITICAL COMPONENTS FIRST AT CLOSEST
LENGTH














USUALLY THE MORE TIME YOU TAKE IN COMPONENT PLACEMENT, THE LESS TIME YOU WILL NEED FOR ROUTING
WHICH PLACEMENT IS BETTER AND WHY ??? (L OR R)


25

WHICH PLACEMENT IS BETTER AND WHY ??? (L OR R)




WHICH PLACEMENT IS BETTER AND WHY ??? (L OR R)

26

PCB Inspector
START THE PCB INSPECTOR.
THIS IS ONE OF THE MOST USEFUL AND TIME SAVING FEATURES IN ALTIUM

27

HOLD DOWN SHIFT AND
CLICK BOTH R14 AND C10
THE PCB INSPECTOR
SHOWS TWO OBJECTS ARE
DISPLAYED/SELECTED.













CHANGE THE LAYER FROM
TOP TO BOTTOM, AND ALL SELECTED
OBJECTS ARE IMMEDIATELY CHANGED TO
THE BOTTOM LAYER

THIS CHANGE MOVED THE COMPONENT
PADS FROM THE TOP OF THE BOARD TO THE
BOTTOM OF THE BOARD AND MIRRORED
THEM

28

WE CAN NOW PLACE R14 AND C10 UNDERNEATH THE USB CONNECTOR
AND MAKE THE CONNECTION FROM THE BOTTOM OF THE BOARD.
NOTICE THE PADS ARE BLUE (COLOR CODE BOTTOM LAYER), THIS LETS YOU
KNOW THAT THESE COMPONENTS ARE ON THE BOTTOM OF THE BOARD




















Component Placement
PLACE THE THREE DECOUPLING CAPACITORS ON THE
BOTTOM LAYER, AND POSITION THEM AS CLOSE TO THE
POWER PINS AS POSSIBLE AS SHOWN RIGHT


29

THE CURRENT LIMITING RESISTORS CAN BE PLACE ON THE
BOTTOM OF THE BOARD (UNDER THE FT232 CHIP)

THE RX AND TX INDICATOR LEDS SHOULD BE PLACED ON
THE TOP OF THE BOARD










THIS IS BEGINNING TO LOOK VERY
CRAMPED AND HARD TO SEE THINGS
WHICH ARE OVERLAPPING.
WE DONT CARE WHERE THE COMPONENT
LABELS (TOP OVERLAY) GO, AND WILL
POSITION THEM LAST, SO THEY ARE JUST
GETTING IN THE WAY RIGHT NOW

30

CLICK ON THE LS AT THE LEFT OF THE LIST OF LAYERS. THIS IS TO CHANGE THE ACTIVE LAYER SET (VISIBLE LAYERS)

THIS WILL BRING UP A SCREEN LIKE THAT ON THE RIGHT. CHANGE THE SETTING TO SIGNAL LAYERS


THIS SHOWS ONLY SIGNAL LAYERS OR
LAYERS THAT CONDUCT ELECTRICITY AND HIDES
THE REST OF THE LAYERS THAT WE DONT CARE
ABOUT AT THE MOMENT.
MOST OF ROUTING IS BEST DONE WITH THE
SIGNAL LAYERS LAYERSET ACTIVE


IT IS MUCH EASIER TO LOOK FOR LINES THAT
CROSS OVER HERE AND MAKE CHANGES WITH
COMPONENT PLACEMENT.

NOTE: BE CAREFUL WHEN PLACING COMPONENTS IN THIS MODE. THE TOP
OVERLAY (SILKSCREEN) IS SOMETIMES USED FOR COMPONENT BOUNDARIES AND YOU
MIGHT PLACE A COMPONENT INSIDE THE BOUNDARY OF ANOTHER PART

PLACE THE REST OF THE COMPONENTS HOWEVER YOU WANT TO



31

Routing
NOW WE NEED TO MAKE ELECTRICAL CONNECTIONS BETWEEN THE COMPONENTS
CLICK THE ICON TO INTERACTIVELY ROUTE CONNECTIONS
NOTE: WHICHEVER LAYER IS ACTIVE, THE TRACE WILL BEING ON THAT LAYER





MAKE A CONNECTION BETWEEN TWO COMPONENTS AS SHOWN.

NOTICE THAT THE WIRE ITSELF IS ASSOCIATED WITH THE NET VCC


BY LOWERING THE MASKED OBJECTS FACTOR IN
THE MASK LEVEL IN THE BOTTOM RIGHT CORNER,
WHEN YOU CLICK ON A PAD TO WIRE, SUCH AS
VCC, IT WILL DULL OUT THE OTHER CONNECTIONS
TO MAKE IT EASIER TO SEE WHERE THE
CONNECTIONS NEED TO GO
32

YOU SHOULD ADJUST THIS SO YOU CAN EASILY SEE THE
HIGHLIGHTED NET, BUT STILL SEE THE OUTLINES OF THE OTHER
PADS















PRESS THE TAB KEY WHILE ROUTING AND YOU CAN CHANGE THE WIDTH OF THE TRACE FOR THAT PARTICULAR NET, AND
SPECIFIC HOLE SIZES. MAKE VCC 15 MILS


33

NOTICE THE NEW VCC TRACE IS 15 MILS THICK










TRY TO ROUTE THIS BOARD USING MOSTLY PERPENDICULAR
TRACES.
FOR EXAMPLE, USE THE BOTTOM LAYER FOR HORIZONTAL
TRACES, AND THE TOP LAYER FOR VERTICAL TRACES. THIS WILL
MAKE THE ROUTING MUCH EASIER (AT THE EXPENSE OF MORE
HOLES)






THE CONNECTION ON THE RIGHT IS A DIFFERENTIAL PAIR AT A
HIGH FREQUENCY.
DIFFERENTIAL PAIRS SHOULD BE KEPT CLOSER TOGETHER
ALTHOUGH YOU ARE USING AN ORTHOGONAL METHOD OF
LAYING OUT THE BOARD, CRITICAL NETS DO NOT NEED TO
APPLY.
TRY TO KEEP THE LAYER CHANGES AND DISCONTINUITIES TO A
MINIMUM FOR CRITICAL LINES


34

AS A GENERAL RULE FOR
RIGHT NOW, YOU WANT TO
MAKE THE TRACES ABOUT AS
LARGE AS YOU CAN MAKE
THEM.
WHY ?











WHEN THE USB CONNECTOR IS
COMPLETE, THERE SHOULD BE FOUR
TRACES COMING FROM THE USB
INTERFACE TO THE REST OF THE CIRCUIT
VCC
GND
TX
RX

35

THE TX AND RX TRACES FROM THE FT232
CHIP TO THE REST OF THE CHIP CAN BE
RELATIVELY HIGH SPEED (1 MB/S)
FOR REASONS WE WILL GO OVER LATER, THIS
MEANS WE SHOULD TRY TO MAINTAIN THE
SAME GEOMETRY THROUGHOUT THE TRACE.
(DONT VARY THE WIDTH)













WHEN THE ROUTING IS COMPLETE, YOU SHOULD HAVE SOMETHING THAT LOOKS
LIKE THE PICTURE TO THE RIGHT.

VCC AND GND CONNECTIONS ARE NOT ALL COMPLETE THOUGH.

WE WILL WORK ON VCC FIRST

36

IN THE LEFT-HAND DROP DOWN BOX AT THE TOP, SELECT VCC. THIS WILL HIGHLIGHT THE VCC NET

NOTE: THE BOX TO THE RIGHT WILL HIGHLIGHT AND JUMP TO A PARTICULAR COMPONENT.



THE VCC NET IS HIGHLIGHTED AND THERE ARE THREE RATSNEST WIRES
THAT NEED TO BE CONNECTED.

MAKE THE CONNECTIONS TO CONNECT ALL THE VCCS TOGETHER

REPEAT THE PROCESS FOR GND

37

WHEN THE ROUTING IS COMPLETE, THERE SHOULD BE NO MORE RATSNEST
WIRES


WE MUST RUN A DRC (DESIGN RULE CHECK) TO MAKE SURE THERE ARE NO
ERRORS.

CLICK TOOLS > DESIGN RULE CHECK











UNCHECK THE BOX TO CREATE A REPORT FILE
CLICK RUN DESIGN RULE CHECK



IF THERE ARE NO ERRORS, YOU SHOULD GET AN EMPTY
MESSAGE BOX LIKE BELOW


38

CHANGE THE LAYER SET
BACK TO ALL LAYERS
AND VIEW THE ENTIRE
BOARD.
AS YOU CAN SEE, WE
HAVE A LOT OF WASTED
AREA, SO THIS GIVES US A
CHANCE TO RESIZE THE
BOARD












CLICK AND DRAG THE PINK LINE TO
THE RIGHT TO THE LEFT, LEAVING
ABOUT 50 MILS SPACING BETWEEN
THE PINK LINE AND THE
TRACES/COMPONENTS

39

NOTICE THE DIMENSIONS ARE AUTOMATICALLY FIXED TO THE
NEW DISTANCE BETWEEN THE ARROWS

REPEAT THIS PROCESS WITH THE BOTTOM PINK LINE













THE BOARD SHOULD LOOK SOMETHING LIKE THIS.

PRESS AND HOLD SHIFT AND CLICK TO SELECT ALL FOUR PINK LINES


40

CLICK
DESIGN > BOARD SHAPE > DEFINE FROM SELECTED OBJECTS


THE BOARD SHOULD NOW BE RESIZED TO THE NEW DIMENSIONS

NOTE: THE PINK LINE IS A SPECIAL LINE CALLED A KEEP-OUT LAYER. THIS IS TO
PREVENT PLACING COMPONENTS TOO CLOSE TO THE EDGE OF THE BOARD


41

Cleaning Up The Design
NOW WE SHOULD CLEAN UP THE DESIGN. THE TOP OVERLAY (SILKSCREEN) ARE OVERLAPPING VIAS SO THEY WONT
SHOW UP WELL, THE FONTS ARE TOO BIG, AND THE SPACING IS TOO CLOSE TOGETHER



RIGHT CLICK ON ANY OF THE TOP OVERLAY (SUCH AS D1) AND CLICK FIND SIMILAR OBJECTS


UNDER STRING TYPE- DESIGNATOR, CHANGE FROM ANY TO SAME. THIS WILL SELECT ALL DESIGNATORS ON THE
BOARD

42

YOU CAN SEE THAT ALL THE COMPONENT
DESIGNATORS ARE SELECTED, AND NOTHING ELSE
THE PCB INSPECTOR SHOWS THAT 99 OBJECTS ARE
SELECTED

CHANGE THE TEXT KIND FROM STROKE FONT TO
TRUE TYPE














THE CHANGES ARE IMMEDIATELY MADE AND ALL 99
DESIGNATORS ARE CHANGED FROM STROKE FONT TO
TRUE TYPE FONT.

THE REDUCED SIZE AND CLEANER FONT TYPE ALREADY
MAKES THE BOARD LOOK A LOT BETTER

43

P4 AND P5 ARE NOT VERY INTUITIVE TO THE END USER AND SHOULD PROBABLY BE CHANGED TO SOMETHING MORE
DESCRIPTIVE.
ALSO, THE 8-BIT LED DISPLAY CAN ALSO BE CHANGED TO BIT0, BIT1, ETC OR 1,2,4,8, SO A USER CAN EASILY ADD
THE BINARY NUMBERS


GO BACK TO THE SCHEMATIC, AND CHANGE P5 TO LED INPUT

CHANGE P1 TO PORTB
CHANGE P4 TO PORTD
CHANGE P2 TO PORTC
CHANGE P3 TO ISP (IN CIRCUIT SERIAL PROGRAMMING)
CHANGE D9 TO TX
CHANGE D10 TO RX

WE ARE MAKING 7 CHANGES TO COMPONENT NAMES HERE
44

CLICK DESIGN > UPDATE PCB DOCUMENT DEV BOARD

AS A RESULT OF CHANGING THE COMPONENT NAMES,
SOME NETS CHANGED ALSO. APPLY ALL CHANGES EXCEPT
ADDING THE ROOM


THE CHANGES HAVE TAKEN PLACE AND NOW WE EACH CONNECTOR IS MORE DESCRIPTIVE
THIS METHOD CAN ALSO BE USED TO CHANGE PCB FOOTPRINTS, ETC

45

YOU CAN MAKE THE FONT LARGER OR IN BOLD, OR CHANGE THE FONT ITSELF IF YOU WANT TO, JUST DOUBLE CLICK THE
TEXT TO BRING UP THE MENU

THESE CONNECTORS WILL HAVE PIN HEADERS ON THEM ONCE ASSEMBLED, SO THE PIN 1 INDICATOR WITH THE
RECTANGULAR PAD WILL BE INVISIBLE TO US. WE NEED TO ADD A BETTER PIN 1 INDICATOR.


CLICK THE PLACE ARC BY EDGE
PLACE AN ARC ANYWHERE ON THE BOARD
DOUBLE CLICK ON THE ARC TO GET THE PROMPT BELOW, CHANGE:
RADIUS = 5 MIL
WIDTH = 10 MIL
START ANGLE = END ANGLE = 0
LAYER = TOP OVERLAY
46

COPY & PASTE THE ARC (DOT) AND PLACE NEXT TO THE PIN 1S FOR THE 10 PIN HEADERS
















WE SHOULD CREATE TWO NEW BOARD LAYER SETS.
ONE WHERE ONLY ITEMS ON THE TOP OF THE BOARD ARE
VISIBLE

ONE WHERE ITEMS ON THE BOT OF THE BOARD ARE VISIBLE

CLICK THE LS AT THE BOTTOM OF THE SCREEN AND CLICK
BOARD LAYER SETS





47

CLICK NEW SET IN THE BOTTOM LEFT
CLICK MAKE EMPTY

















NAME THE SET TOP
BOARD
CHECK THE FOLLOWING
BOXES:
TOP LAYER
TOP OVERLAY
MULTI-LAYER

48

CREATE ANOTHER NEW SET
CALLED BOT BOARD
CHECK THE VIEW FROM
BOTTOM SIDE
CHECK THE FOLLOWING BOXES:
TOP LAYER
TOP OVERLAY
MULTI-LAYER












SELECT THE TOP BOARD FROM THE LAYER SET.
THIS IS WHAT THE REAL BOARD WILL LOOK LIKE FROM THE TOP
LOOKING DOWN WITHOUT THE DEFAULT SUPERMAN ABILITY TO
SEE THROUGH ALL THE LAYERS












49

THIS IS THE BEST VIEW TO MOVE THE TOP
OVERLAY/SILKSCREEN LAYERS AROUND TO MAKE SURE IT
WILL LOOK GOOD WHEN YOU ARE DONE.
NOTE: YOU SHOULD AVOID THE HOLES WITH THE TOP
OVERLAY, BUT DO NOT WORRY IF THE TOP OVERLAY IS
ON TOP OF A TRACE













I HAVE MOVED R10 AND R11 INDICATORS TO A
LOCATION WITH LESS CLUTTER AND WITHOUT BEING
BLOCKED BY A VIA.


50

THIS IS ALSO THE TIME WHERE YOU SHOULD OPTIMIZE YOUR TRACES.

THE TRACE ON THE TOP IMAGE LOOKS SILLY AND WAS PROBABLY
DONE BECAUSE OF OPTICAL INTERFERENCE WITH THE BOTTOM LAYER
VIEWING ONLY THE TOP LAYER CAN HELP SPOT ERRORS EASILY AND
MAKE A CLEAN AND PROFESSIONAL LOOKING PCB












SET THE ACTIVE LAYER SET TO THE BOT LAYER YOU MADE
PERFORM THE SAME OPTIMIZATIONS AS WITH THE TOP LAYER


51

THE IMAGE TO THE LEFT SHOWS A DRC ERROR BECAUSE THE POLARITY MARKING FOR THE CAPACITORS ARE TOO CLOSE
TOGETHER. THIS IS NOT A REAL ERROR AND WE DONT CARE ABOUT IT
THE IMAGE ON THE RIGHT DOES NOT FLAG FOR AN ERROR, BUT THE BOTTOM OVERLAY FOR C1 WILL NOT SHOW UP
PROPERLY BECAUSE OF THE LOCATION OF THE VIA.
DOES ANYONE NOTICE ANYTHING ELSE WRONG WITH THE IMAGE TO THE RIGHT ???


IS ANYTHING WRONG WITH THE BOTTOM OVERLAY IN THIS PICTURE ?




52

OUR BOARD LOOKS OK, BUT THERE IS A LOT OF UNUSED SPACE



















WE WILL ADD WHAT IS CALLED A COPPER POUR OR POLYGON POUR TO FILL IN THE EMPTY AREAS

CLICK THE POLYGON PLANE ICON AS SHOWN TO THE RIGHT
CHANGE NET TO GND
53

CLICK ABOUT 50-100 MILS AWAY FROM THE EACH CORNER AND THEN RIGHT CLICK
THIS WILL BEGIN THE POLYGON CALCULATION AND PLACEMENT.

NOTE: FOR LARGE DESIGNS THIS CAN TAKE HOURS


















NOTICE HOW THE POLYGON POUR WILL AVOID A NET THAT IS DIFFERENT THAN THE NET
ASSIGNED TO IT.


IT WILL PUT COPPER EVERYWHERE POSSIBLE THAT DOESNT CREATE A VIOLATION
54

ON NETS THAT THERE IS A CONNECTION (GND), YOU
CAN SEE IT HANDLES IT EXACTLY THE SAME AS ANY
OTHER NET, BUT HAS A FEW SHORT CONNECTORS
THAT CONNECT THE PAD/HOLE TO THE POUR












REPEAT THIS PROCESS ON THE BOTTOM LAYER OF
THE BOARD, ALSO CONNECTING TO GND















THATS THE PCB BASICALLY FINISHED
NEXT WEEK PRODUCING DOCUMENTATION AND ENGINEERING OUTPUTS