1

2

EXPERIMENT-1
AIM- Design Of Basic Gates
SOFTWARE USED- XILINX ISE 8.1
(A) AND Gate

AND Gate Schematic


AND gate RTL Schematic


AND Gate Test Bench Waveform






3

EXPERIMENT-1
AIM- Design Of Basic Gates
SOFTWARE USED- XILINX ISE 8.1
(A) AND Gate


















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity andgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end andgate;

architecture Behavioral of andgate is
begin
process(a,b)
begin
if (a='1' and b='1') then
c<='1';
else c<='0';
end if;
end process;

end Behavioral;


4

(B) OR Gate

OR Gate Schematic


OR Gate RTL Schematic


OR Gate Test Bench Waveform




5

(B) OR Gate





















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity orgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end orgate;

architecture or_df of orgate is
begin
y<=a or b;
end or_df;


6

(C) NOT Gate


NOT gate Schematic


NOT Gate RTL Schematic


NOT Gate Test Bench Waveform








7

(C) NOT Gate





















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity notgate is
Port ( a : in STD_LOGIC;
y : out STD_LOGIC);
end notgate;

architecture not_df of notgate is

begin
y<= not a;
end not_df;


8

EXPERIMENT-2
AIM- Design Of Universal Gates
SOFTWARE USED- XILINX ISE 8.1
(A) NAND Gate

Nand Gate Schematic

NAND Gate RTL Schematic

NAND Gate Test Bench Waveform





9

EXPERIMENT-2
AIM- Design Of Universal Gates
SOFTWARE USED- XILINX ISE 8.1
(A) NAND Gate


















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nandgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end nandgate;

architecture nand_df of nandgate is

begin

y<= a nand b;
end nand_df;


10

(B) NOR Gate

NOR Gate Schematic


NOR Gate RTL Schematic


NOR Gate Test Bench Waveform






11

(B) NOR Gate
























library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity norgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end norgate;

architecture nor_df of norgate is

begin
y<=a nor b;

end nor_df;


12


EXPERIMENT-3
AIM- Design Of 2:1 Multiplexer
SOFTWARE USED- XILINX ISE 8.1

2:1 Multiplexer Schematic

2:1 Multiplexer Schematic Contituent

2:1 Multiplexer RTL Schematic

2:1 Multiplexer Test Bench Waveform


13



EXPERIMENT-3
AIM- Design Of 2:1 Multiplexer
SOFTWARE USED- XILINX ISE 8.1


















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux_2_1 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC);
end mux_2_1;

architecture Behavioral of mux_2_1 is

begin
process(s,a)
begin
if s='0' then
y<=a(0);
else
y<= a(1);
end if;
end process;
end Behavioral;

14

EXPERIMENT-4
AIM- Design Of 2 to 4 Decoder
SOFTWARE USED- XILINX ISE 8.1

Schematic Of 2 to 4 decoder

Constituent Of 2 to 4 Decoder

RTL Schematic Of 2 to 4 Decoder

Testbench Waveform Of 2 to 4 Decoder



15

EXPERIMENT-4
AIM- Design Of 2 to 4 Decoder
SOFTWARE USED- XILINX ISE 8.1



























library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder2_4 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder2_4;

architecture Behavioral of decoder2_4 is

begin
with a select y <=
"0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others ;

end Behavioral;


16

EXPERIMENT-5
AIM- Design Of Half Adder and Full Adder
SOFTWARE USED- XILINX ISE 8.1
(A) Half Adder

Schematic of Half Adder

RTL Schematic Of Half Adder

Constituent Of Half Adder

Test Bench waveform Of Half Adder

17

EXPERIMENT-5
AIM-Design of Half Adder and Full Adder
SOFTWARE USED- XILINX ISE 8.1
(A) Half Adder




















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity halfadder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end halfadder;

architecture ha_df of halfadder is

begin
s<= a xor b;
c<= a and b;

end ha_df;

18

(B) Full Adder

Schematic Of Full Adder

RTL Schematic Of Full Adder

Full Adder Constituent

Full Adder Constituent

Full Adder Test Bench Waveform

19

(C) Full Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end fulladder;

architecture Behavioral of fulladder is

begin
s<= a xor b xor cin;
c<= (a and b) or (b and cin) or (a and cin);
end Behavioral;

20

EXPERIMENT-6
AIM-Design of 3:8 Decoder
SOFTWARE USED-XILINX ISE 8.1

3:8 Decoder Schematic

3:8 Schematic Constituent

3:8 Decoder RTL Schematic

3:8 Decoder Test Bench Waveform

21

EXPERIMENT-6
AIM- Design of 3:8 decoder
SOFTWARE USED- XILINX ISE 8.1




















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder3_8 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder3_8;

architecture dec3_8df of decoder3_8 is

begin
with a select y <=
"00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others ;

end dec3_8df;


22

EXPERIMENT-7
AIM- Design of Binary to Gray Code Convertor.
SOFTWARE USED- XILINX ISE 8.1

Schematic Of Binary to Gray Code Convertor


Schematic Of Binary to Gray Code Convertor Constituent


Schematic of RTL Contituent Of Binary to Gray Code Convertor


Test bench Waveform Of Binary To Gray Code Convertor


23

EXPERIMENT-7
AIM- Design of Binary to Gray Code Convertor.
SOFTWARE USED- XILINX ISE 8.1
























library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BINtoGRAY is
Port ( BIN : in STD_LOGIC_VECTOR (3 downto 0);
GRAY : out STD_LOGIC_VECTOR (3 downto 0));
end BINtoGRAY;

architecture Behavioral of BINtoGRAY is

begin
GRAY(3)<=BIN(3);
GRAY(2)<=BIN(3) xor BIN(2);
GRAY(1)<=BIN(2) xor BIN(1);
GRAY(0)<=BIN(1) xor BIN(0);

end Behavioral;


24

EXPERIMENT-8
AIM- Design of Binary to BCD Convertor
SOFTWARE USED- XILINX ISE 8.1

Schematic Of Binary To BCD Convertor

Schematic Of Binary To BCD Convertor Constituent

RTL Schematic Of Binary To BCD Convertor








25

EXPERIMENT-8
AIM- Design of Binary to BCD Convertor.
SOFTWARE USED- XILINX ISE 8.1
























library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BINtoBCD is
Port ( BIN : in STD_LOGIC_VECTOR (3 downto 0);
BCD : out STD_LOGIC_VECTOR ( downto 0));
end BINtoBCD;

architecture Behavioral of BINtoBCD is
begin
process(BIN)
begin
if(BIN="0000")then
BCD<="00000000";
elsif(BIN="0001")then
BCD<="00000001";
elsif(BIN="0010")then
BCD<="00000010";
elsif(BIN="0011")then
BCD<="00000011";
elsif(BIN="0100")then
BCD<="00000100";
elsif(BIN="0101")then
BCD<="00000101";
elsif(BIN="0110")then
BCD<="00000110";
elsif(BIN="0111")then
BCD<="00000111";

26


Testbench Waveform Of Binary To BCD Convertor



27

























elsif(BIN="1000")then
BCD<="00001000";
elsif(BIN="1001")then
BCD<="00001001";
elsif(BIN="1010")then
BCD<="00010000";
elsif(BIN="1011")then
BCD<="00010001";
elsif(BIN="1100")then
BCD<="00010010";
elsif(BIN="1101")then
BCD<="00010011";
elsif(BIN="1110")then
BCD<="00010100";
elsif(BIN="1111")then
BCD<="00010101";
end if;
end process;
end Behavioral;

28

EXPERIMENT-9
AIM- Design of 8:3 Priority Encoder
SOFTWARE USED- XILINX ISE 8.1

Schematic Of 8:3 Priority Encoder

RTL Schematic Of 8:3 Priority Encoder

Test Bench Waveform Of 8:3 Priority Encoder



29

EXPERIMENT-9
AIM- Design of 8:3 Priority Encoder
SOFTWARE USED- XILINX ISE 8.1






















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity priority_encoder_8_3 is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0);
Z : out STD_LOGIC);
end priority_encoder_8_3;

architecture Behavioral of priority_encoder_8_3 is

begin
process(A)
begin
if A(7)='1' then
Y<="111";
Z<='1';
elsif A(6)='1' then
Y<="110";
Z<='1';
elsif A(5)='1' then
Y<="101" ;
Z<='1';
elsif A(4)='1' then
Y<="100" ;
Z<='1';
elsif A(3)='1' then
Y<="011" ;
Z<='1';

30



31













elsif A(2)='1' then
Y<="010" ;
Z<='1';
elsif A(1)='1' then
Y<="001" ;
Z<='1';
elsif A(0)='1' then
Y<="000" ;
Z<='1';
else
Z<='0';
end if;
end process;
end Behavioral;

32

EXPERIMENT-10
AIM- Design of Flip Flops
SOFTWARE USED- XILINX ISE 8.1
(i) SR FLIP FLOP

Schematic of SR Flip FLOP


RTL Schematic OF SR Flip Flop


Test Bench Waveform Of SR Flip Flop








33

EXPERIMENT-10
AIM- Design of Flip Flops
SOFTWARE USED- XILINX ISE 8.1
(i) SR Flip Flop





























library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity srflipflop is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC;
QN : inout STD_LOGIC);
end srflipflop;

architecture Behavioral of srflipflop is

begin
process (S,R,Q,QN)
begin
Q <= R NOR QN;
QN <= S NOR Q;
end process;
end Behavioral;


34


(ii) JK Flip Flop

Schematic Of JK Flip Flop

RTL Schematic Of JK Flip Flop

Test Bench Waveform Of JK Flip Flop











35

(ii) JK Flip Flop
































library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jkflipflop is
Port ( J : in STD_LOGIC:='0';
K : in STD_LOGIC:='1';
CLK : in STD_LOGIC;
Q : inout STD_LOGIC:='0';
QN : inout STD_LOGIC:='1');
end jkflipflop;

architecture Behavioral of jkflipflop is

begin
process(J,K,CLK)
begin
if(CLK='1' and CLK'event) then
if (J='0' and K='0') then
Q<=Q;
QN<=QN;
elsif(J='1' AND K='0') then
Q<='1';
QN<='0';
elsif(J='0' and K='1') then
Q<='0';
QN<='1';
else
Q<=not Q;
QN<=not QN;
end if;
end if;
end process;
end Behavioral;

36

(iii) D Flip Flop

Schematic Of D Flip Dlop

RTL Schematic Of D Flip Flop

Test Bench Waveform Of D Flip Flop







37

(iii) D Flip Flop






















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dflipflop is
Port ( D : in STD_LOGIC:='0';
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
QN : out STD_LOGIC);
end dflipflop;

architecture Behavioral of dflipflop is

begin
process (CLK)
begin
if (CLK = '1' and CLK'EVENT) then
Q <= D;
QN <= NOT D;
end if;
end process;
end Behavioral;


38

(iv) T Flip Flop

Schematic Of T Flip Flop

RTL Schematic Of T Flip Flop

Test Bench Waveform Of T Flip Flop



39

(iv) T Flip Flop





















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tflipflop is
Port ( T : in STD_LOGIC:='0';
CLOCK : in STD_LOGIC;
Q : inout STD_LOGIC:='1';
QN : inout STD_LOGIC:='0');
end tflipflop;

architecture Behavioral of tflipflop is

begin
process(CLOCK,T)
begin
if (CLOCK = '1' and CLOCK'event) then
if (T='1')then
Q <= NOT Q;
QN <= NOT Q after 0.5ns;
else
Q <= Q;
QN <= NOT Q after 0.5ns;
end if;
end if;
end process;
end Behavioral;

40

EXPERIMENT-10
AIM- Design of Shift Register with shift right, shift left, load and synchronous
reset.
SOFTWARE USED- XILINX ISE 8.1

Schematic Of Shift Register

Schematic Constituent of Shift Register


41


EXPERIMENT-10
AIM- Design of Shift Register with shift right, shift left, load and synchronous
reset.
SOFTWARE USED- XILINX ISE 8.1


















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shiftregister is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
s_in : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
lsh_rsh : in STD_LOGIC;
b : out STD_LOGIC_VECTOR (7 downto 0);
s_out : out STD_LOGIC);
end shiftregister;

architecture Behavioral of shiftregister is

begin
process(clk,clr,s_in,a)
variable temp:STD_LOGIC_VECTOR(7 downto 0);
begin
temp := a;
if clr = '1' then
b<="00000000";
s_out<='0';
elsif clk'event and clk = '1' then
if lsh_rsh = '0' then
s_out<= temp(7);
temp:= temp(6 downto 0) & s_in;
b<= temp;

42


RTL Contituent of Shift Register

Test Bench Waveform Of Shift Register


43


elsif lsh_rsh = '1' then
s_out<=temp(0);
temp:= s_in & temp(7 downto 1);
b<=temp;
end if;
end if;
end process;

end Behavioral;