MIPS32

Instruction Set
Quick Reference
RD DESTINATION REGISTER
RS, RT SOURE OPERAND REGISTERS
RA RETURN ADDRESS REGISTER !R3"#
P PROGRAM OUNTER
A $%&'IT AUMU(ATOR
(O, )I AUMU(ATOR (O* !A3"+,# AND )IG) !A$3+32# PARTS
SIGNED OPERAND OR SIGN E-TENSION
UNSIGNED OPERAND OR .ERO E-TENSION
++ ONATENATION O/ 'IT /IE(DS
R2 MIPS32 RE(EASE 2 INSTRUTION
DOTTED ASSEM'(ER PSEUDO&INSTRUTION
P(EASE RE/ER TO MIPS32 ARCHITECTURE FOR PROGRAMMERS VOLUME II:
THE MIPS32 INSTRUCTION SET /OR OMP(ETE INSTRUTION SET IN/ORMATION0
ARITHMETIC OPERATIONS
ADD RD, RS, RT RD 1 RS 2 RT !O3ER/(O* TRAP#
ADDI RD, RS, ONST"$ RD 1 RS 2 ONST"$

!O3ER/(O* TRAP#
ADDIU RD, RS, ONST"$ RD 1 RS 2 ONST"$

ADDU RD, RS, RT RD 1 RS 2 RT

(O RD, RS RD 1 OUNT(EADINGONES!RS#
(. RD, RS RD 1 OUNT(EADING.EROS!RS#
(A RD, (A'E( RD 1 ADDRESS!(A'E(#
(I RD, IMM32 RD 1 IMM32
(UI RD, ONST"$ RD 1 ONST"$ 44 "$
MO3E RD, RS RD 1 RS
NEGU RD, RS RD 1 5RS
SE'
R2
RD, RS RD 1 RS6+,

SE)
R2
RD, RS RD 1 RS"7+,

SU' RD, RS, RT RD 1 RS 5 RT !O3ER/(O* TRAP#

SU'U RD, RS, RT RD 1 RS 5 RT
SHIFT AND ROTATE OPERATIONS
ROTR
R2
RD, RS, 'ITS7 RD 1 RS'ITS75"+, ++ RS3"+'ITS7
ROTR3
R2
RD, RS, RT RD 1 RSRT%+,5"+, ++ RS3"+RT%+,
S(( RD, RS, S)I/T7 RD 1 RS 44 S)I/T7
S((3 RD, RS, RT RD 1 RS 44 RT%+,
SRA RD, RS, S)I/T7 RD 1 RS

88 S)I/T7
SRA3 RD, RS, RT RD 1 RS

88 RT%+,
SR( RD, RS, S)I/T7 RD 1 RS

88 S)I/T7
SR(3 RD, RS, RT RD 1 RS

88 RT%+,
LOGICAL AND BIT-FIELD OPERATIONS
AND RD, RS, RT RD 1 RS 9 RT
ANDI RD, RS, ONST"$ RD 1 RS 9 ONST"$

E-T
R2
RD, RS, P, S RS 1 RSP2S&"+P

INS
R2
RD, RS, P, S RDP2S&"+P 1 RSS&"+,
NOP NO&OP
NOR RD, RS, RT RD 1 :!RS ; RT#
NOT RD, RS RD 1 :RS
OR RD, RS, RT RD 1 RS ; RT
ORI RD, RS, ONST"$ RD 1 RS ; ONST"$

*S')
R2
RD, RS RD 1 RS23+"$ ++ RS3"+2% ++ RS6+, ++ RS"7+<
-OR RD, RS, RT RD 1 RS RT
-ORI RD, RS, ONST"$ RD 1 RS ONST"$

CONDITION TESTING AND CONDITIONAL MOVE OPERATIONS

MO3N RD, RS, RT I/ RT = ,, RD 1 RS
MO3. RD, RS, RT I/ RT 1 ,, RD 1 RS
S(T RD, RS, RT RD 1 !RS

4 RT

# > " + ,
S(TI RD, RS, ONST"$ RD 1 !RS

4 ONST"$

# > " + ,
S(TIU RD, RS, ONST"$ RD 1 !RS

4 ONST"$

# > " + ,
S(TU RD, RS, RT RD 1 !RS

4 RT

# > " + ,
MULTIPLY AND DIVIDE OPERATIONS
DI3 RS, RT (O 1 RS

? RT

; = RS

MOD RT

DI3U RS, RT (O 1 RS

? RT

; = RS

MOD RT

MADD RS, RT A 21 RS

RT

MADDU RS, RT A 21 RS

RT

MSU' RS, RT A @1 RS

RT

MSU'U RS, RT A @1 RS

RT

MU( RD, RS, RT RD 1 RS

RT

MU(T RS, RT A 1 RS

RT

MU(TU RS, RT A 1 RS

RT

ACCUMULATOR ACCESS OPERATIONS

M/)I RD RD 1 )I
M/(O RD RD 1 (O
MT)I RS )I 1 RS
MT(O RS (O 1 RS
JUMPS AND BRANCHES (NOTE: ONE DELAY SLOT)
' O//"< P 21 O//"<

'A( O//"< RA 1 P 2 <, P 21 O//"<

'EQ RS, RT, O//"< I/ RS 1 RT, P 21 O//"<

'EQ. RS, O//"< I/ RS 1 ,, P 21 O//"<

'GE. RS, O//"< I/ RS A ,, P 21 O//"<

'GE.A( RS, O//"< RA 1 P 2 <B I/ RS A ,, P 21 O//"<

'GT. RS, O//"< I/ RS 8 ,, P 21 O//"<

'(E. RS, O//"< I/ RS C ,, P 21 O//"<

'(T. RS, O//"< I/ RS 4 ,, P 21 O//"<

'(T.A( RS, O//"< RA 1 P 2 <B I/ RS 4 ,, P 21 O//"<

'NE RS, RT, O//"< I/ RS = RT, P 21 O//"<

'NE. RS, O//"< I/ RS = ,, P 21 O//"<

D ADDR2< P 1 P3"+2< ++ ADDR2<

DA( ADDR2< RA 1 P 2 <B P 1 P31:28 ++ ADDR28

DA(R RD, RS RD 1 P 2 <B P 1 RS

DR RS P 1 RS
LOAD AND STORE OPERATIONS
(' RD, O//"$!RS# RD 1 MEM<!RS 2 O//"$

('U RD, O//"$!RS# RD 1 MEM<!RS 2 O//"$

() RD, O//"$!RS# RD 1 MEM"$!RS 2 O//"$

()U RD, O//"$!RS# RD 1 MEM"$!RS 2 O//"$

(* RD, O//"$!RS# RD 1 MEM32!RS 2 O//"$

#
(*( RD, O//"$!RS# RD 1 (OAD*ORD(E/T!RS 2 O//"$

#
(*R RD, O//"$!RS# RD 1 (OAD*ORDRIG)T!RS 2 O//"$

#
S' RS, O//"$!RT# MEM<!RT 2 O//"$

# 1 RS6+,
S) RS, O//"$!RT# MEM"$!RT 2 O//"$

# 1 RS"7+,
S* RS, O//"$!RT# MEM32!RT 2 O//"$

# 1 RS
S*( RS, O//"$!RT# STORE*ORD(E/T!RT 2 O//"$

, RS#
S*R RS, O//"$!RT# STORE*ORDRIG)T!RT 2 O//"$

, RS#
U(* RD, O//"$!RS# RD 1 UNA(IGNEDEMEM32!RS 2 O//"$

#
US* RS, O//"$!RT# UNA(IGNEDEMEM32!RT 2 O//"$

# 1 RS
ATOMIC READ-MODIFY-WRITE OPERATIONS
(( RD, O//"$!RS# RD 1 MEM32!RS 2 O//"$

#B (INF
S RD, O//"$!RS#
I/ ATOMI, MEM32!RS 2 O//"$

# 1 RDB
RD 1 ATOMI > " + ,
oGHriIJt K 2,,6 MIPS TecJnoLoIies, Inc0 ALL riIJts reserMeN0 MD,,7$7 ReMision ,"0,,
REGISTERS
, Oero ALPQHs eRuQL to Oero
" Qt AsseSTLer teSGorQrHB useN TH tJe QsseSTLer
2&3 M,&M" Return MQLue froS Q function cQLL
%&6 Q,&Q3 /irst four GQrQSeters for Q function cQLL
<&"7 t,&t6 TeSGorQrH MQriQTLesB neeN not Te GreserMeN
"$&23 s,&s6 /unction MQriQTLesB Sust Te GreserMeN
2%&27 t<&tU TPo Sore teSGorQrH MQriQTLes
2$&26 k,&k" FerneL use reIistersB SQH cJQnIe uneVGecteNLH
2< IG GLoTQL Gointer
2U sG StQck Gointer
3, fG?s< StQck frQSe Gointer or suTroutine MQriQTLe
3" rQ Return QNNress of tJe LQst suTroutine cQLL
DEFAULT C CALLING CONVENTION (O32)
Stack Management
TJe stQck IroPs NoPn0
SuTtrQct froS WsG to QLLocQte LocQL storQIe sGQce0
Restore WsG TH QNNinI tJe sQSe QSount Qt function eVit0
TJe stQck Sust Te <&THte QLiIneN0
MoNifH WsG onLH in SuLtiGLes of eiIJt0
Function Parameters
EMerH GQrQSeter sSQLLer tJQn 32 Tits is GroSoteN to 32 Tits0
/irst four GQrQSeters Qre GQsseN in reIisters WQ,@WQ30
$%&Tit GQrQSeters Qre GQsseN in reIister GQirs+
(ittLe&enNiQn SoNe+ WQ"+WQ, or WQ3+WQ20
'iI&enNiQn SoNe+ WQ,+WQ" or WQ2+WQ30
EMerH suTseRuent GQrQSeter is GQsseN tJrouIJ tJe stQck0
/irst "$ THtes on tJe stQck Qre not useN0
AssuSinI WsG PQs not SoNifieN Qt function entrH+
TJe "
st
stQck GQrQSeter is LocQteN Qt "$!WsG#0
TJe 2
nN
stQck GQrQSeter is LocQteN Qt 2,!WsG#, etc0
$%&Tit GQrQSeters Qre <&THte QLiIneN0
Return Values
32&Tit QnN sSQLLer MQLues Qre returneN in reIister WM,0
$%&Tit MQLues Qre returneN in reIisters WM, QnN WM"+
(ittLe&enNiQn SoNe+ WM"+WM,0
'iI&enNiQn SoNe+ WM,+WM"0
READING THE CYCLE COUNT REGISTER FROM C
unsigned mips_cycle_counter_read()
{
unsigned cc;
asm volatile("mfc0 %0, $9" : "r" (cc));
return (cc !! ");
#
ASSEMBLY-LANGUAGE FUNCTION EXAMPLE
$ int asm_ma%(int a, int &)
$ {
$ int r (a ! &) ' & : a;
$ return r;
$ #
(te%t
(set nomacro
(set noreorder
(glo&al asm_ma%
(ent asm_ma%
asm_ma%:
move $v0, $a0 $ r a
slt $t0, $a0, $a" $ a ! & '
)r $ra $ return
movn $v0, $a", $t0 $ if yes, r &
(end asm_ma%
C / ASSEMBLY-LANGUAGE FUNCTION INTERFACE
$include !stdio(*+
int asm_ma%(int a, int &);
int main()
{
int % asm_ma%("0, "00);
int y asm_ma%(,00, ,0);
printf("%d %d-n", %, y);
#
ATOMIC READ-MODIFY-WRITE EXAMPLE
atomic_inc:
ll $t0, 0($a0) $ load lin.ed
addiu $t", $t0, " $ increment
sc $t", 0($a0) $ store cond/l
&e01 $t", atomic_inc $ loop if failed
nop
INVOING MULT AND MADD INSTRUCTIONS FROM C
int dp(int a23, int &23, int n)
{
int i;
long long acc (long long) a203 4 &203;
for (i "; i ! n; i55)
acc 5 (long long) a2i3 4 &2i3;
return (acc ++ 6");
#
ACCESSING UNALIGNED DATA
NOTE: ULW AND USW AUTOMATICALLY GENERATE APPROPRIATE CODE
LITTLE-ENDIAN MODE BIG-ENDIAN MODE
(*R RD, O//"$!RS#
(*( RD, O//"$23!RS#
(*( RD, O//"$!RS#
(*R RD, O//"$23!RS#
S*R RD, O//"$!RS#
S*( RD, O//"$23!RS#
S*( RD, O//"$!RS#
S*R RD, O//"$23!RS#
ACCESSING UNALIGNED DATA FROM C
typedef struct
{
int u;
# __attri&ute__((pac.ed)) unaligned;
int unaligned_load(void 4ptr)
{
unaligned 4uptr (unaligned 4)ptr;
return uptr7+u;
#
MIPS SDE-GCC COMPILER DEFINES
__mips MIPS ISA !1 32 for MIPS32#
__mips_isa_rev MIPS ISA ReMision !1 2 for MIPS32 R2#
__mips_dsp DSP ASE eVtensions enQTLeN
_89:;<= 'iI&enNiQn tQrIet PU
_89:;<> (ittLe&enNiQn tQrIet PU
_89:;_?@AB_CPU TQrIet PU sGecifieN TH 7marc*CPU
_89:;_CDE<_CPU PiGeLine tuninI seLecteN TH 7mtuneCPU
NOTES
MQnH QsseSTLer GseuNo&instructions QnN soSe rQreLH useN
SQcJine instructions Qre oSitteN0
TJe cQLLinI conMention is siSGLifieN0 ANNitionQL ruLes QGGLH
PJen GQssinI coSGLeV NQtQ structures Qs function GQrQSeters0
TJe eVQSGLes iLLustrQte sHntQV useN TH G coSGiLers0
Most !Tut not QLL# MIPS Grocessors increSent tJe cHcLe counter
eMerH otJer cHcLe0 PLeQse cJeck Hour Grocessor NocuSentQtion0
MD,,7$7 ReMision ,"0,, oGHriIJt K 2,,6 MIPS TecJnoLoIies, Inc0 ALL riIJts reserMeN0