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STA Documentation

The parser converts a Verilog file into a temporary netlist file with a .tmp extension. The temporary netlist file describes the gate level netlist including gate indices, node names, levels, gate types, and fan-ins and fan-outs. The gate delay file specifies delays for different gate types and numbers of inputs. Primary input and output early/late and required times are provided in a separate file. The makefile generates a parser executable to create the temporary netlist and an STA executable to perform static timing analysis and output the top critical paths based on the netlist, delay, and I/O timing files.

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47 views

STA Documentation

The parser converts a Verilog file into a temporary netlist file with a .tmp extension. The temporary netlist file describes the gate level netlist including gate indices, node names, levels, gate types, and fan-ins and fan-outs. The gate delay file specifies delays for different gate types and numbers of inputs. Primary input and output early/late and required times are provided in a separate file. The makefile generates a parser executable to create the temporary netlist and an STA executable to perform static timing analysis and output the top critical paths based on the netlist, delay, and I/O timing files.

Uploaded by

ram.prasath.19881869
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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STA documentation

Parser: The parser is reused from the ESFF parser provided. The verilog le is converted to temporary
netlist with extenstion tmp. An example c17.tmp looks like
p0 N1 1
4
p1 N2 2
4
5
p2 N3 1
5
q3 N4 3
6
a4 NAND2_1 1 6 2 1
0 1
6
a5 NAND2_2 1 6 2 1
1 2
6
a6 NAND2_3 2 6 2 1
4 5
3
N1
NAND2_1
N2
NAND2_2
N3
NAND2_3
N4
As it can be seen from the gure p and q used to indicate primary inputs and outputs respectively.
a is used to indicate gates. the next eld indicates the index in the array. The following string indicates
the name of the node in the verilog le. The next eld indicates the level of the node in the level ordered
list, followed by type of gate and #fanins and #fanouts. e.g a6 NAND2 3 2 6 2 1 reads as gate with
index 6 and type NAND(6) in level 2 with 2 input and 1 output nodes.
The gatedelay le has the delay specication for dierent types of gates described using type and
number of inputs.
The input eat, lat and req eat and req lat of the primary inputs and primary outputs are provided
in the le < benchmark > pi e l at in the order in which they occur in the verilog le.
Usage: make generates two executable parser and sta.
parser generates the temporary netlist format.
usage: ./parser c17.v > c17.tmp
sta takes 3 inputs .tmp le, benchmark pi e l at le and #critical paths to display.
usage: ./sta c17.tmp c17 pi e l at 10
generates 10 late and early slack critical paths.

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