Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips

Tilmann St ohr, Markus Alt, Asmus Hetzel, J urgen Koehl

IBM Entwicklung GmbH, Sch onaicher Strae 220, 71032 B oblingen, Germany
E-Mail: [email protected]
Abstract
As chip size and design density increase, coupling effects (crosstalk)
between signal wires become increasingly critical to onchip timing
and even functionality. A method is presented to analyze crosstalk
while taking into account timing relationship and timing criticality
between coupling wires. The method is based upon the geometrical
layout of the wires (adjacency), the signal slopes on the wires (circuit
driving capability) and timing considerations.
Based on these wire characteristics, a pattern driven routing tool
imbeds the crosstalk critical nets in non-adjacent wiring tracks for
crosstalk avoidance. The pattern driven routing capability may also
be used for rerouting crosstalk critical nets of an already existing
routing for crosstalk reduction.
The crosstalk analysis and the routing tool described in this paper
were used in three generations of VLSI processor chip designs for
IBMs S/390 computers, always resulting in crosstalk-resistant hard-
ware.
1 Introduction
Crosstalk is a wellknown phenomenon at all levels of electronic
packaging from system level cables through wires on printed cir-
cuit boards and multichipmodules to chip level routing. It is an
electromagnetic effect due to coupling capacitances and inductances
between currents in electrical conductors.
Crosstalk causes undesired signal noise to be coupled from an active
line (aggressor) into a quiet line (victim). Depending on its magni-
tude, the induced noise onto the victim may inuence the timing be-
haviour of the victim signal by increasing its setup time. It may even
cause failure by inducing false pulses or causing false signal levels
(see reference [cat]) which may be propagated through the circuit.
With increasing integration density and reduced cycle times, these
effects become more visible and more destructive, so they need to be
handled more carefully. Crosstalk needs to be considered in particu-
lar on VLSI chips with submicron structures and todays large die
sizes.
A good overview of the electrical parameters determining crosstalk
can be found in reference [vit].
c
Various transient analysis techniques to estimate noise are avail-
able. In most cases, the problem can be modeled as a linear circuit.
Specialized linear model reduction techniques (see references [pil]
and [fel]) help minimize model complexity and computational cost,
as applied in references [she] and [dev].
A practical way to reduce computational cost and time is to separate
the model extraction from the crosstalk analysis. The results of the
model extraction for a small number of coupled wires with different
wire geometries is repeatedly applied to the physical routing data of
the VLSI chip. Both capacitive and inductive coupling are taken into
account for the model extraction. A complete RLCextraction of the
chip routing is avoided.
Based on that approach, we present new methods for the analysis, re-
duction and avoidance of crosstalk, used successfully on VLSI logic
chips developed by IBM B oblingen for three generations of S/390
processor chips. The program package described in this paper ap-
plies to IBMs most recent S/390 Parallel Enterprise Server Gen-
eration 4. The overall design methodology is presented in refer-
ence [koe]. Table 1 lists the key characteristics of the technology
used.
technology name SA12
base technology CMOS / 5 layers of metal
eff. channel length
eff
= 0.18 m
min. feature size 0.63 m wire width / spacing
clock cycle typically 4.5 ns
signal slopes 0.4 ns
application IBM System/390 G4 Server
Table 1: Properties of technology used
The method for crosstalk analysis described in this paper is based
on a 6step approach. Step 1 is executed only once for each new
technology, while steps 2 through 6 represent the chip dependent
crosstalk analysis:
1. extract the electrical parameters for a base set of adjacent wire
congurations, like 2 to 3 coupled lines with different widths
and spacings
2. extract the geometry of the complete chip routing spacings
3. calculate the adjacency lengths between a chosen wire segment
(victim) and its neighbors (aggressors) considering the wire
widths and spacings
4. determine the circuits driving victim and aggressor lines and,
from the circuits timing rules, calculate the effective output
resistances inuencing the signal slopes and the amount of cou-
pled noise
5. consider the lower acceptable noise margin for exceptionally
noisesensitive input pins (e. g. passgate inputs) versus the
standard CMOS inputs of logic circuits
1
6. read the switching times of victim and aggressor lines from
the chips timing report and disregard all timinguncritical wire
adjacencies
2 Crosstalk on VLSI Chips
As the structures become smaller, die sizes become larger, and cir-
cuits become faster, crosstalk between two wires on a chip increases.
In a simplied model, coupling between two lines can be considered
a capacitive voltage divider (see gure 1). Reference [gal] describes
a crosstalk estimation and analysis technique based on capacitive
coupling only.
However, inductive coupling cannot be neglected and is therefore
considered in the modeling in section 3. For inductances, a similar
voltage divider can be modeled. The value of the mutual inductance
versus the intrinsic inductance of coupled wires determines the mag-
nitude of the induced noise.
Higher integration causes larger mutual capacitance and
smaller intrinsic capacitance of a line, both worsening cross-
talk. The same is valid for the inductive coupling as the mutual in-
ductance in particular grows signicantly with denser struc-
tures.
Neglecting the output resistances of the driving circuits leads
to incorrect model behaviour. The coupled noise would then be in-
dependent of the coupling length as all , , and are
proportional to the wire length. Taking the output resistances
and the input capacitances of the receiving circuits into account, the
model in gure 1 shows a crosstalk voltage nearly proportional to the
coupling wire length, as expected.
aggressor
victim
Figure 1: Simple model of coupled wires
Larger die sizes increase the average wire length on a chip, thus in-
creasing the potential for excessive crosstalk. Newtechnologies offer
faster circuits producing faster switching output signals. This causes
higher amplitudes of coupled noise across and in particular
(see gure 1), again increasing the potential for excessive crosstalk.
Crosstalk may occur between both horizontally and vertically adja-
cent wires, i. e. wires on the same routing layer are coupling to each
other as well as wires on different routing layers running on top of
each other.
Wires with diagonal adjacency must be considered as well (see
gure 2). With increasing distance between aggressor and victim in
any direction, the induced coupled noise decreases drastically.
The wire widths heavily inuence the coupling, as all components of
the line model in gure 1 ( , , and, in particular, ) depend
on the conductor width.
horizontal adjacency: A1V A5V
vertical adjacency: A3V
diagonal adjacency: A2V A4V
V = victim
A1 ... A5 = aggressors
A1 V A5
A2 A3 A4
Figure 2: Chip cross section with adjacent wires
3 Modeling of Crosstalk
In addition to the geometrical arrangement of the wires, other impor-
tant factors inuence the crosstalk noise coupled into the victim net.
Two of these are the driving capability of the circuits on the nets and
the timing relationship between aggressor and victim. The following
subsections discuss these factors in detail.
3.1 Extraction of Wire Parameters
A sufciently exact crosstalk analysis of a given chip routing to pre-
dict potential crosstalk problems is strongly dependent on the avail-
ability of an accurate model for coupled lines and of analytical meth-
ods for capacitance and inductance calculation. Detailed analyses
of capacitance modeling on chip level are found in references [sak]
and [del], the latter also including inductances. As mentioned in the
introduction (section 1), full chip level extractions of electrical pa-
rameters are not practical due to data volume. In our approach, only
a small number of adjacency congurations are being investigated in
a rst step.
The noise voltage induced into a single victimwire is calculated with
a detailed wire model. AS/X, an internal IBM circuit simulation tool
similar to SPICE (see reference [spc]) is used for the analysis. It
simulates both the circuits driving victim and aggressor lines as well
as the coupled lines based on their R, C and Lcomponents. A
line is broken down into several hundred pieces of discrete RLC
components representing the wire behaviour.
A 3D extraction tool is used to determine the lines C and L
components. 3D in this context means considering not only ad-
jacent lines on the same layer of the chip, but also crossing lines on
the layers above and below as well as the wider power lines on all
layers. The power lines as current return paths have a great inu-
ence onto the selfinductance of chip wires and therefore onto the
inductive coupling.
For the SA12 CMOS technology described in table 1, an induced
peak noise of / 3 is allowed. This leaves sufcient margin for
additional power noise. Detailed AS/X circuit simulations show that
noise above this peak value at a circuits input pin causes the circuit
to propagate the noise pulse. Avoiding noise propagation ensures the
correct functioning of the circuits in a logic path.
The acceptable height of a noise pulse at a circuits input pin is de-
pendent on its width (duration). The DC noise limit is used as the
worst case lower limit for noise of any duration. Thus, noise pulse
width may be neglected without missing any critical coupling.
2
3.2 Geometry
The approach in this paper is to determine the coupling between a
pair of horizontally directly adjacent wires (minimum spacing, min-
imum width) in a rst step. Other geometries (different spacing and
width, vertical and diagonal neighbourhood) are then calculated rela-
tive to that reference. A critical maximumlength for direct
adjacency is determined such that the receiving circuit on the victim
wire will not switch due to a noise peak.
Using AS/X to simulate the typicalcase scenario consisting
of identical driving circuits on aggressor and victim line,
= 8 mm is found for the SA12 technology.
For other wire geometries, relative coupling factors are in-
troduced which describe the induced peak noise compared to di-
rect horizontal adjacency for a given coupled length. Direct hori-
zontal adjacency causes the highest coupling of all possible geome-
tries ( ). Therefore, all relative coupling factors are
.
distance width width relative
victim aggressor coupling
H: factor
V:
1 H 1 1 1.00
1 H 2 2 0.89
2 H 1 1 0.69
2 H 2 2 0.63
3 H 1 1 0.52
3 H 2 2 0.47
2 V 1 1 0.56
2 V 2 2 0.68
Note: H = horizontal adjacency
V = vertical adjacency
Table 2: Relative coupling factors (wire)
The relative coupling factors of different wire geometries are shown
in table 2. This table lists only some example values from the com-
plete list of all wire geometries used by a given routing tool and of
all possible vertical and diagonal adjacencies. For wire distances of
4 channels, the relative coupling factors are so small that crosstalk
can be neglected for all practical purposes.
The relative coupling factor for a given geometry means that
the induced noise is smaller by the factor compared to the
same length of directly adjacent wires, or that the acceptable adja-
cency length for that geometry is longer by 1 / .
A victim may have, of course, more than one aggressor coupling into
it. Without looking into the timing of the signals, all aggressors must
be considered switching simultaneously in a worst case scenario. As
the induced noise depends on the product of the geometrical adjacent
length and the geometry weight factor from table 2, these so
called weighted adjacent lengths can simply be summed to get the
total weighted adjacent length coupling into a victim.
If the total weighted adjacent length exceeds the above dened value
, the victim net is considered critical. Excessive
crosstalk is very likely to occur on this net. Critical nets are han-
dled by additional measures described in sections 5 and 6.
3.3 Circuit Driving Capability
The driving capabilities of the circuits on the aggressor and victim
nets are represented by their output resistances. A smaller output
resistance causes a steeper slope of a switching signal at this pin.
An aggressor net driven by a circuit with small output resistance has
steep signal slopes, and more noise will be coupled into an adjacent
victimwire. Avictimdriven by a circuit with small output resistance,
however, will be less sensitive for crosstalk, as the low damping
resistor at the wire input will allow less noise to be induced via the
mutual capacitance and inductance between aggressor and victim.
AS/X simulations have been run with circuits of different driving ca-
pability on the same pair of coupled lines. The circuit output devices
have been varied from very small to very large transistor sizes on
both victim and aggressor, resulting in corresponding effective out-
put resistances from 100 to 1000 . Table 3 shows the cou-
pled noise relative to the nominal case with identical aggressor and
victim driving circuits.
As the geometrical arrangement of the coupled lines is expressed in
relative coupling factors, the circuit output resistance is taken into
account in a similar manner. The (geometrically) weighted adja-
cent lengths are weighted additionally with the relative coupled peak
noise factor as listed in table 3.
aggressor victim relative relative
output output peak noise peak noise
resistance resistance from AS/X according to
simulations equation (1)
1095 1095 0.93 1.00
452 452 1.00 1.00
147 147 1.05 1.00
1095 147 0.35 0.34
452 147 0.62 0.61
147 452 1.61 1.61
147 1095 2.82 2.90
Table 3: Relative coupling factors (circuit)
For simple modeling of the inuence of the output resistances, a
simple mathematical equation is chosen, which efciently and very
closely approximates the discrete values in table 3. AS/X results serve
as base to derive an equation on a best t basis.
Equation (1) approximates the exact value from the above
mentioned AS/X simulations within 10% for the SA12 technology.
(1)
This approximation equation is found under the condition
= 1.0 for identical circuits on both coupled wires with
= . For identical victim and aggressor
circuits, a maximum allowed adjacent length =8 mm
is found with AS/X simulations, as mentioned in section 3.2.
For different wire geometries (width and spacing) and different
driving circuits (output resistance) the weighted adjacent length
is dened. It is calculated from the geometrical adjacent
length (victim and aggressor running in parallel) according
to equation (2).
(2)
Hence, the total crosstalk induced into a victim without considering
timing is the sum of the contributions of all aggressors. Under the
assumption of a peak noise of / 3 for 8 mm coupled length of
directly adjacent wires, the total noise voltage of all aggressor
segments is calculated according to equation (3).
3
(3)
Equation (3) implies a peak noise of less than if the following
condition is satised:
(4)
The terms in equations (3) and (4) may all be associated with differ-
ent aggressor nets. Some of them, however, may result from differ-
ent segments belonging to the same aggressor net. All these adjacent
segments are added up in the same way according to equation (4).
3.3.1 Comparison to Analytical Model
The dependency of the coupled peak noise from the circuit output
resistances and the coupled wire length is derived in another way in
reference [vit] based on a crosstalk model as shown in gure 3, using
an analytical noise model.
aggressor
victim
Figure 3: Capacitive model (Tcircuit) of coupled wires
The aggressor line is driven by a voltage source (stepping
) with an intrinsic resistance of , the victim line is
connected to ground via a quiet circuit represented by just its intrin-
sic resistance .
The two coupled lines are modeled by the discrete values of their
intrinsic capacitances and and the mutual capacitance
between the two lines.
To enhance the model described in reference [vit], the longitudinal
resistances and of the lines are added. They are
modeled by the resistors on either side of the discrete capacitors with
half the longitudinal resistance of the lines each.
According to reference [vit], the peak noise voltage of the model in
gure 3 is
(5)
Equation (5) was run through the mathematical tool Maple to ver-
ify the values in table 3. The simplied model in gure 3 together
with the step generator, as opposed to the behaviour of a real driv-
ing circuit, is somewhat pessimistic. Indeed, the peak noise voltages
derived from this analytical model are always between 10% and 20%
higher than in AS/X simulations. This is a satisfying conrmation of
the coupled line model chosen in this paper.
3.4 Noise Sensitivity of Input Pins
In some cases, the threshold voltage of certain circuit input pins may
be lower than for the typical CMOS library elements. Pins with
lower threshold voltages may be used to decrease switching times.
Either the transistors are designed to have lower gate threshold volt-
ages or pass gate inputs may be used, e. g. for latches. These lower
noise margins imply a higher sensitivity to crosstalk.
The crosstalk analysis tool in this paper easily allows for these lower
noise margins by another correction factor to the maximum allowed
adjacency length. Like the weight factors for different geometries
(see section 3.2) and for different circuit driving capability (see sec-
tion 3.3), another weight factor is introduced for nets connected to
noise sensitive pins.
The acceptable physical adjacency length of a victim wire de-
creases proportionally to the noise margin of the most sensitive
input pin connected. The noise margin of a standard CMOS in-
put pin allowing sufciently for additional power noise is given as
/ 3 .
Victim nets having pins with lower noise margin are
weighted with a factor . The weighted adjacency length
increases with allowing less physical adjacency length.
(6)
The total weighted adjacency length of a victim dened in equa-
tion (4) is multiplied with . This value must be less than the
reference critical length ( =8 mm for SA12).
(7)
for all i aggressor segments.
3.5 Timing Behaviour
Many of the nets identied as crosstalk critical when considering
geometry (see subsection 3.2) and circuit output resistance only (see
subsection 3.3) can further be eliminated by considering their tim-
ing. Most of our CMOS VLSI chips analyzed for crosstalk are syn-
chronous designs, i. e. they have paths starting at a latch output, pass-
ing through combinatorial logic only and ending at another latchs
input. A signal is launched by a clock pulse, propagated through
its path and is caught at the receiving latch by another, synchronous
clock pulse. On some chips, however, different asynchronous clock
domains are implemented.
A victim net may be discarded from the list of critical nets if the
crosstalk pulse induced occurs early enough before the signals latest
allowable switching time. To be able to specify early enough, the
following descriptors of the timing behaviour are dened:
arrival time: time when a logic signal
reaches its nal state in a clock cycle
required arrival time: time when a logic
signal must have reached its nal state be-
fore getting latched
slack time: time reserve between arrival
time and required arrival time
clock pulse: time when the logic signals are
latched at the receiving latches
safety margin: time to allow induced noise
to fade away ( signal slope time)
A victim net with a positive slack value has this extra time
period until it is latched after propagation through its path. Hence, a
4
noise pulse induced within that time period or earlier is not harmful.
Figure 4 shows the relationship of the above dened timing values in
a timing diagram.
coupled noise
Figure 4: Timing descriptors for coupled nets
As the induced noise pulse on the victim net needs some time to
fade away, a time margin is introduced. From experience,
is comparable to the duration of the signal slope on the
aggressor line. Therefore, has been chosen for
the SA12 technology.
In summary, equation (8) describes the condition for a victims stable
state not to be inuenced by a coupling aggressor. All nets which
fulll this relation may be discarded as critical crosstalk problems.
This optional function is called the timing lter, applied to each
pair of aggressor and victim lines.
(8)
There are two situations in which equation (8) may not be applied
to discard critical nets. First, clock nets usually switching at ex-
actly the critical latching time are always considered critical aggres-
sors and critical victims (a noisy clock pulse causes functional prob-
lems). Second, the induced noise may occur unpredictably at any
point in time between coupled nets belonging to different clock do-
mains (asynchronous nets).
4 Analysis of Crosstalk
Based on the model presented in section 3, a C program called
CrossTalk implements the complete presented method. The pro-
gramreads a parameter le containing the relative (geometrical) cou-
pling factors as dened in section 3.2 and the critical length
as given in section 3.3.
The chip data, in particular all net segments and the driving circuits
of all nets, is read from the design datasets. These are a number
of binary les corresponding to the incore data structures of the
logical and physical chip data. Further, a circuit list containing
the output resistances of all circuits is read. The timing data (slacks,
arrival times, clock cycle times) of the design is read from the net
le generated in a preceding timing analysis run.
CrossTalk extracts all adjacent segments as given in the pa-
rameter table (e. g. up to a distance of 3 channels). It then nds the
driving circuits for the coupling nets and calculates the correspond-
ing relative coupling factor according to equation (1). With
these data, the weighted adjacent lengths according to equation (2)
are calculated and added up. All victim nets with a total weighted
adjacent length below are discarded then from the list
of critical nets.
In a nal step, the timing lter discards the timing uncritical nets
which satisfy equation (8). As already mentioned, this timing lter
does not discard any clock nets from the report, nor does it discard
adjacencies between nets belonging to different clock domains.
In the SA12 technology of table 1, a fully populated 12.8 mm chip
has been analyzed using CrossTalk. The design contains 342,000
nets with 3,490,000 wire segments. To show the advantages of con-
sidering geometric, electrical and timing properties of the nets, the
results of three scenarios of CrossTalk are listed in table 4.
scenario critical CPU memory
(active option, nets time used
cumulative) found
1) geometry only 246 9:56 623
2) circuit 97 10:40 679
3) timing of nets 46 14:41 683
Table 4: Comparison of different program scenarios
Introducing the dependency on the output resistance of the circuits
in scenario 2) of table 4, and activating the timing lter in scenario
3), reduces the number of incorrectly identied critical adjacencies
signicantly. This minimizes the effort to eliminate the critical nets
reported. Strategies to solve the remaining problems are discussed in
section 5 and section 6.
CrossTalk reports the nets found as critical in a comprehensive report
le which shows all characteristics of the coupling nets, i. e. whether
a net is victim or aggressor, the weighted adjacent length of the cou-
pling segments, its clock domain (cycle time), its timing descriptors
(see section 3.5) and its driving circuits output resistance. Heres a
small example of a report le:
5 Reduction of Crosstalk
The coupling nets remaining as critical after applying the meth-
ods described in sections 3 and 4 must be modied to reduce their
criticality without worsening crosstalk between other nets.
A straightforward net length minimizer proved to work fairly well
for the chips based on the SA12 CMOS technology with up to
12.8 mm die size and more than 340,000 nets. A net optimizing
program reroutes the remaining critical nets reported by CrossTalk
trying to minimize the net length and the number of vias used. This
results in straightening out those nets while the local routing tool
5
originally tried to minimize the use of routing resources, inserting
many edges and bends into a wire.
This procedure requires little CPU time and reduces the number of
crosstalk critical nets considerably. A subsequent crosstalk analysis
proves that only a small number of these nets remain critical on all
chips mentioned above. These remaining nets can be checked man-
ually, using AS/X to exclude all worst case assumptions of the model
used in this paper or they can be manually rerouted, e. g. by moving
adjacent nets apart for a fraction of their adjacent length.
Rerouting crosstalk critical nets using this basic net optimization
method is admittedly not deterministic but has proven to work well in
practice, in particular on the last two generations of VLSI processor
chips designed in technologies earlier than SA12.
A deterministic reroute method is applied to the high density SA
12 chips of the latest generation. It uses pattern driven routing
as described in section 6 to reroute all nets considered critical by a
preceding crosstalk analysis of the completely routed chip.
The victim nets found to be critical are collected in a class Victims,
the aggressor nets in a class Aggressors. Both classes are associated
with special wire codes wire aggressor and wire victim, respectively.
These wire codes are assigned to routing patterns (shape classes)
disallowing a wire aggressor to be routed adjacently to a wire victim
and vice versa.
The pattern driven routing tool now attempts to reroute all victims
and aggressors according to the given routing patterns. If one or
more segments of a wire fail rerouting, the original routing will be
kept to avoid generating incomplete nets.
On a very dense chip however, this may cause some crosstalk prob-
lems to remain unsolved by this automated reroute procedure. Ad-
ditional effort by the designer will then be necessary. A proven
method of manual rerouting is jogging of a long victim net be-
tween or around its aggressor wires to reduce the inuence of one
single aggressor. An algorithmic solution of this manual approach is
presented in reference [jhj].
Figure 5 shows an overview of the proposed design ow for crosstalk
reduction of an existing chip routing.
placement and
detailed routing
crosstalk
analysis
classes of critical nets
pattern driven
rerouting
crosstalk
analysis
remaining critical nets
designer review
and manual reroute
Figure 5: Process Flow for Crosstalk Reduction
Running the above pattern driven routing method on the already
mentioned 342,000 nets VLSI processor chip, major crosstalk im-
provements can be achieved as listed in table 5.
A reduction of the number of victims to zero by using automated
rerouting is not possible on this very dense chip. In any case, the
manual effort to improve or remove the remaining critical adjacen-
cies is minimized, as the maximum weighted adjacency length for
the worst victim net is also reduced.
rerouting victim aggressor maximum
applied to nets nets total adj.
found found length [ m]
1) none 46 95 10309
2) victims only 32 57 10145
3) victims +aggressors 21 34 6902
Table 5: Results of critical nets rerouting
Further effort is being invested into the pattern driven routing tool
which capable of routing any number of wires grouped into classes
following certain constraints. This new method generates an initial
chip routing attempting to avoid crosstalk altogether.
6 Avoidance of Crosstalk
For the increasing coupling effects in future technologies, the simple
reroute strategy described in section 5 may no longer be sufcient.
Instead, a method is needed that avoids crosstalk problems while
routing. In contrast to more general approaches interacting with all
aspects of the chip physical design (as discussed in reference [kir])
the method in this paper simply applies a detailed routing tool con-
trolled by crosstalk constraints.
Prior papers like reference [gao] dealt with the improvements of
channel routing algorithms capable of generating routing solutions
that satisfy the relative positions of the chip wires. In contrary to our
proposal, even short crosstalk uncritical wires were considered and
affected, resulting in a reduction of the routing capability within a
given area.
As crosstalk is strictly a local phenomenon it is handled within de-
tailed routing (local routing) rather than in global routing. The nal
arrangement of all wire segments is determined within detailed rout-
ing, where the crosstalk relevant parameters (see section 3) can be
extracted. Moreover, the detailed router usually has sufcient free-
dom for the assignment of wire segments to channels to avoid the
most critical coupling congurations. However, detailed routing is
typically one of the most CPU time and memory intensive tasks in
physical chip design. Therefore, the detailed router is guided by sim-
ple geometrical restrictions for crosstalk avoidance rather than by a
complete complex electrical wire model.
XRouter is a program package designed for highperformance VLSI
chip routing developed at the Research Institute for Discrete Math-
ematics of the University of Bonn, Germany. It uses a two stage
global / detailed routing scheme. Global routing restricts the area
where a net may be routed to a small part of the chip based on
Steiner tree constructions and congestion estimates. Detailed rout-
ing is based on a sequential ripup and reroute approach.
XRouter is capable of performing detailed pattern routing. The un-
derlying principle assumes that any piece of metal (shape) placed
on the wiring grid is associated with a certain class (shape class).
Using input parameters, up to 32 shape classes may be dened. Each
shape class contains predened shape types (e. g. blockages, pin ar-
eas, power rails) associated with nets or net parts of certain groups.
Shape classes dene patterns to be avoided during the nal routing.
For crosstalk purposes, two shape classes and
6
may be dened. Crosstalk sensitive wires are associated with
, nonsensitive wires with . Then the pattern
prevents the router from putting crosstalk sensitive wires into adja-
cent channels, while the pattern
FREE
prevents the router from putting crosstalk sensitive wires on both
sides of an unused channel. Two sensitive wires on both sides of
another segment associated with , however, are permitted
due to additional shielding.
Arbitrary forbidden patterns may be specied individually for all
planes and separately for horizontal and vertical adjacencies. Ad-
ditionally, patterns can be restricted to apply only to the global part
of the nets to improve pin accessibility.
XRouter is designed to handle a large number of different patterns
simultaneously. It uses a multilevel pattern evaluation scheme in-
volving several lookup and caching steps. Therefore, performance
is mostly affected by the size of the patterns, i. e. the number of chan-
nels they involve. The solvability of the routing task (e. g. contra-
dicting patterns given by the user) signicantly inuences the perfor-
mance, while the number of patterns given does not limit solvability
and performance considerably.
The following general approach will be used for crosstalk avoidance
with pattern routing in future chip physical designs:
Determine potentially critical victim and aggressor nets by
analysis of circuit driving capability, wire width and estimated
routing length, e. g. by Steiner tree approximations from the
preceding placement step or the global router.
Divide the critical nets into orthogonal sets whenever pos-
sible, i. e. group these nets so that crosstalk is critical only
between members of the same group. This is useful in par-
ticular for multistageclock designs where nets are known to
be quiet in certain time intervals.
Code shape classes to disallow nets of the same group to run in
parallel without sufcient distance or intermediate shields.
Run the detailed router under the terms of these additional
shape classes.
Not all potential crosstalk problems on any given chip can be treated
this way, but for the majority of nets the allowed neighbourhood is
controllable by patterns to sufciently avoid coupling. More details
about this pattern driven router and its usage are found in refer-
ences [kru] and [het].
Figure 6 shows an overview of the proposed design ow for crosstalk
avoidance during initial routing of a chip.
The shape classes of long nets are generated by the netlength esti-
mate of the global router in gure 6. They contain all potential ag-
gressor nets in (global connections longer than a crit-
ical value, e. g. 2 mm for SA12) and all potential victim nets in
(global connections longer than a critical value, e. g. 5 mm
for SA12). The following routing patterns are dened to prevent ad-
jacent routing of victim to victim, victim to aggressor and aggressor
to victim:
Controlling the pattern driven router in the above way using 2
shape classes and 3 patterns will generate a routing optimized for
little crosstalk. On a very dense chip, however, not too many nets
should be included into the 2 shape classes. Local wiring conges-
tion will cause the router to generate long detours for some of the
specied nets. Chip timing will be affected, even though crosstalk
problems will be avoided. Additionally, the run time of the router
will increase unacceptably up to a magnitude in CPU time.
Good percentages for the mentioned 342,000 nets VLSI processor
chip are:
less than 5% of all nets in (medium nets)
less than 1% of all nets in (long nets)
To achieve the maximum automated crosstalk minimization, the pro-
cesses of Crosstalk Avoidance and Crosstalk Reduction are com-
bined. The result of the crosstalk analysis in gure 6 is fed into
the pattern driven rerouting of gure 5. This reduces the number
of eventually remaining crosstalk critical adjacencies after the initial
pattern driven detailed routing in gure 6.
placement and
global routing
shape classes of long nets
pattern driven
detailed routing
crosstalk
analysis
remaining critical nets
designer review
and manual reroute
Figure 6: Process Flow for Crosstalk Avoidance
The methods discussed in this section have been applied to the previ-
ously mentioned 342,000 nets VLSI processor chip. Major crosstalk
improvements regarding the number of critical nets are achieved as
listed in table 6. To design a minimum crosstalk VLSI chip, the com-
bination of both crosstalk avoidance routing and crosstalk reduction
rerouting is recommended.
crosstalk victim aggressor maximum
process nets nets total adj.
applied found found length [ m]
1) none 46 95 10309
2) rerouting only 21 34 6902
3) avoidance only 14 35 7567
4) avoidance + rerouting 5 7 6309
5) avoidance + rerouting 1 1 6089
Table 6: Results of crosstalk processes
Run 5) in table 6 shows that it is possible to generate a virtually
crosstalkfree chip design using the described process of crosstalk
avoidance with a subsequent crosstalk reduction. However, this run
needed 5 times more CPU time for the initial pattern driven routing
(82 h versus 18 h). Additionally, the router was forced to use wiring
detours due to an excessive number of nets in the nonadjacent
7
shape classes, resulting in a netlength increase from 194.1 meters
to 195.7 meters.
These wiring detours causing additional RCdelays impact the tim-
ing of some logic paths. The worst slack of all paths went up by
120 ps at a cycle time of 4.5 ns. Therefore, timing always needs to be
considered when running the presented crosstalk process. Maximum
automated crosstalk avoidance with minimum manual effort to re-
move the remaining critical adjacencies can be traded for marginally
slower chip timing.
However, runs 1) through 4) in table 6 resulted in identical chip tim-
ing and similar wiring lengths.
The small amount of remaining critical adjacencies has to be re-
viewed by the chip designer. Subsequent detailed AS/X circuit sim-
ulations of these nets show if the presented method was too pes-
simistic due to some worst case assumptions, or if the adjacen-
cies need additional treatment. Again, jogging of the long victim
nets between or around its aggressor wires reduces the total cou-
pled noise. Running the automated crosstalk avoidance process min-
imizes the manual effort to x the few remaining critical adjacencies.
7 Summary and Conclusions
A new method is presented which comprehensively identies and
corrects onchip crosstalk on large VLSI designs. The extraction
of coupling parameters determined by wire geometry, circuit driv-
ing capability, and timing behaviour is separated in this procedure
from working with the chip specic physical routing data. The im-
plementation of this methodology in a C program runs quickly and
efciently.
Taking the mentioned properties of aggressor and victim nets into
account, a sufciently exact analysis of the crosstalk criticality of
all nets is achieved. No unnecessary worst case assumptions must
be applied as safety margin for side effects not considered in earlier
proposals. Crosstalk analysis can be performed easily, quickly and
with reliable results.
As our CrossTalk program runs on at chip designs, coupling from
and to circuits internal wires will not be handled, as these are not
visible in the chip level design data. In particular very large circuits,
such as array macros, may send or receive coupled noise to or from
chip level wires, respectively. Further enhancements to the analysis
program to cover this kind of crosstalk are under investigation.
The use of a pattern driven router in our chip designs either per-
mits the reduction of onchip crosstalk in an existing routing or the
avoidance of crosstalk in the initial chip routing already.
Rerouting (crosstalk reduction) is driven by shape classes (forbid-
den patterns) applied to nets found by a crosstalk analysis of the
completely routed chip. To guide the pattern driven router from the
beginning on a new chip design (crosstalk avoidance), the neces-
sary net constraints are generated from the global chip routing as
shape classes for long connections.
All chips treated according to this paper are free of any crosstalk
related problems in the hardware, in contrast to the previous chip
generation. One of these chips had a functional problem, discov-
ered as late as during hardware bringup, as no crosstalk anlysis was
available during the design phase. The program CrossTalk was run
on this particular chip to verify the coupling problem, and it pre-
dicted the critical adjacency exactly as observed in hardware. Run-
ning CrossTalk and reducing or avoiding critical adjacencies is es-
sential to get functional hardware.
Acknowledgements
We would like to thank the department members of the VLSI De-
sign Center of the IBM Development Laboratory in B oblingen for
their hints and support for the wording and the contents of this paper.
In particular G unther Hutzl was very helpful about using L
A
T
E
X, and
Erich Klink of the VLSI Packaging and Physical Design depart-
ment layed the basics to initially consider crosstalk an important as-
pect of advanced chip physical design.
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