COMPUTER PROGRAMMING I COMPUTER PROGRAMMING I

(TA C162) ( )
Lecture 10 Combinational Circuits
Todays Agenda
Combinational Circuit Examples
Adder Adder
Multiplexer
Decoder Decoder
PLA
Tuesday, February 02, 2010 2 Biju K Raveendran@BITS Pilani.
Combinational Logic Structures
Examples Examples
Full Adder
Decoder Decoder
Multiplexer (MUX)
Programmable Logic Array Programmable Logic Array
Tuesday, February 02, 2010 3 Biju K Raveendran@BITS Pilani.
Adding two bits: Half Adder
Truth Table:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1 1 1 0 1
Boolean Expressions
S = ((NOTA) AND B) OR (AAND (NOT B))
Limitation: It can add only two bits at a time
S = ((NOT A) AND B) OR (A AND (NOT B))
C = A AND B
Limitation: It can add only two bits at a time
4
Adding Three Bits: Full Adder
4-Bit Full Adder
Requirement: Adds the two bits and a carry
generatedfromthepreviousbit column generated from the previous bit column
Tuesday, February 02, 2010 5 Biju K Raveendran@BITS Pilani.
Full Adder: Truth Table
A B C
in
S C
out
0 0 0 0 0
0 0 1 1 0 0 0 1 1 0
0 1 0 1 0
0 1 1 0 1 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1 1 1 1 1 1
SOP for Sum S = A.B.C + A.B.C + A.B.C + A.B.C
SOP for Carry C = A B C + A B C + A B C + A B C SOP for Carry C = A.B.C + A.B.C + A.B.C + A.B.C
Tuesday, February 02, 2010 6 Biju K Raveendran@BITS Pilani.
Full Adder Logic Implementation
Tuesday, February 02, 2010 7 Biju K Raveendran@BITS Pilani.
Combinational Circuit Example 2
Requirement:
n-bit selector and 2
n
inputs, one output p , p
Output equals one of the inputs, depending on
selector
A B
Selection bits = 1
Inputs =2 (A0, A1)
S
Inputs 2 (A0, A1)
Output is according to the table
S O/P S O/P
0 A0
1 A1
O
1 A1
8
Truth Table
S A1 A0 Y
SOP Expression for Y???
Y= S A1 A0 + S A1 A0 + S A1 A0 + S A B
0 0 0 0
0 0 1 1
Y S .A1 .A0 + S .A1.A0 + S.A1.A0 + S.A.B
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
Lets draw the circuit !!!
1 0 1 0
1 1 0 1
1 1 1 1
It is called as Multiplexer!!!
1 1 1 1
Tuesday, February 02, 2010 9 Biju K Raveendran@BITS Pilani.
4 x 1 MUX Circuit Diagram
4-to-1 MUX 4 to 1 MUX
Tuesday, February 02, 2010 10 Biju K Raveendran@BITS Pilani.
Multiplexer
Many (2
N
) inputs are connected to one output
Uses select lines (N-bits) to determine which ( )
input is connected to the output.
Depending on select lines (N-bits), one of the p g ( ),
2
N
inputs are transferred to output.
MUX (Abbreviation of multiplexer) consists of ( p )
2
N
input lines, N select lines and 1 output line
Example: 2:1 MUX will have 2 input lines, 1 select p p
line and 1 output line
Example 16:1 MUX will have 16 input lines, 4
l t li d 1 t t li select lines and 1 output line
Tuesday, February 02, 2010 11 Biju K Raveendran@BITS Pilani.
Demultiplexer
O i i d M (2
N
) One input is connected to Many (2
N
) outputs
Uses select lines (N-bits) to determine which
t t i t d t th i t output is connected to the input.
Depending on select lines (N-bits), input is
transferred to one of the 2
N
outputs transferred to one of the 2
N
outputs.
DeMUX or DMUX(Abbreviation of demultiplexer)
consists of 1input line N select lines and 2
N
consists of 1input line, N select lines and 2
N
output lines
Example: 1:2 DEMUX will have 1 input line, 1 select Example: 1:2 DEMUX will have 1 input line, 1 select
line and 2 output lines
Example 1:16 DEMUX will have 1 input line, 4 select
16 lines and 16 output lines
Tuesday, February 02, 2010 Biju K Raveendran@BITS Pilani. 12
1:8 demultiplexer p
Tuesday, February 02, 2010 Biju K Raveendran@BITS Pilani. 13
Combinational Circuit Example 3
Lets design a circuit, that takes an n-bit binary
number and produces an output on one of 2
n
number and produces an output on one of 2
n
output lines.
n inputs 2
n
outputs n inputs, 2
n
outputs
Exactly one output is 1 for each possible input
pattern pattern
Example:
L t 2 i t th 4 t t Let n = 2 inputs then 4 outputs
Bit patterns are 00 01 10 11
C ll d D d !!! Called as Decoder !!!
Tuesday, February 02, 2010 14 Biju K Raveendran@BITS Pilani.
What a decoder does?
The n inputs represent a binary number that determines which of
the 2
n
outputs is uniquely true.
A 2 to 4 decoder has A 2-to-4 decoder has
The 2-bit input (S1,S0), and four outputs (A0, A1, A2, A3).
If (S1 S0) =00 (decimal 0), then output A0 is true, and A1, If (S1 S0) 00 (decimal 0), then output A0 is true, and A1,
A2, A3 are all false.
If (S1 S0) = 01, then A1 is true & all other outputs false
If (S1 S0) = 10, then A2 is true & all other outputs false
If (S1 S0) = 11, then A3 is true & all other outputs false
This circuit decodes a binary number into a one-of-four
code.
Tuesday, February 02, 2010 15 Biju K Raveendran@BITS Pilani.
Decoder
Useful in detecting bit patterns Useful in detecting bit patterns
Exactly one of its outputs is 1 and all the rest
are 0s are 0s
One output which is 1corresponds to the
input pattern that decoder is expected to input pattern that decoder is expected to
detect
Tuesday, February 02, 2010 16 Biju K Raveendran@BITS Pilani.
How can you build a 2-to-4 decoder?
We have a truth table, so we can write equations for each
of the four outputs (A0-A3) based on the two inputs (S0- of the four outputs (A0 A3), based on the two inputs (S0
S1).
A0 S1 S0
S1 S0 A0 A1 A2 A3
0 0 1 0 0 0
A0= S1 S0
A1 = S1 S0
0 1 0 1 0 0
1 0 0 0 1 0
A2= S1 S0
A3= S1 S0
1 1 0 0 0 1

Tuesday, February 02, 2010 17 Biju K Raveendran@BITS Pilani.
2-to-4 decoder
S1 S0 A0 A1 A2 A3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
A0=S1.S0
A1=S1.S0

A2=S1.S0
A3=S1 S0 A3=S1.S0
Tuesday, February 02, 2010 18 Biju K Raveendran@BITS Pilani.
Decoder
An N input decoder has 2
N
outputs An N input decoder has 2 outputs
Output
i
is 1 iff the binary value of the N-bit
input is i input is i
At any time, exactly one output is 1, all others
are 0s are 0s
Tuesday, February 02, 2010 19 Biju K Raveendran@BITS Pilani.
PLA
PLA Programmable Logic Arra PLA Programmable Logic Array
Used for implementing any collection of logic
functions functions
Consists of an array of AND gates (called AND
array) followed by an array of OR gates (called OR y) y y g (
array)
Number of AND gates corresponds to the number of
input combinations (rows) in truth table for which at
least one of the output is 1
For N input logic functions we need 2
N
N input ANDgates For N input logic functions, we need 2
N
N input AND gates
Number of OR gates corresponds to the number of
output columns in the truth table ou pu cou s e u abe
Tuesday, February 02, 2010 20 Biju K Raveendran@BITS Pilani.