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FPGA Implementation of High Performance Multipliers

This document discusses the implementation of high-performance multipliers in FPGAs using VHDL. It proposes algorithms for high-speed low-power multipliers. The Booth multiplier reduces the number of partial products generated by a factor of two. The adder avoids unwanted additions to minimize power dissipation. The proposed multiplier can improve speed and reduce power compared to conventional array multipliers. It also examines array, shift-and-add, Booth, pyramid, and modified pyramid multipliers to study their performance tradeoffs.

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rksinha25
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33 views

FPGA Implementation of High Performance Multipliers

This document discusses the implementation of high-performance multipliers in FPGAs using VHDL. It proposes algorithms for high-speed low-power multipliers. The Booth multiplier reduces the number of partial products generated by a factor of two. The adder avoids unwanted additions to minimize power dissipation. The proposed multiplier can improve speed and reduce power compared to conventional array multipliers. It also examines array, shift-and-add, Booth, pyramid, and modified pyramid multipliers to study their performance tradeoffs.

Uploaded by

rksinha25
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FPGA Implementation of high performance Multipliers Using VHDL

Abstract
A multiplier is one of the vital hardware blocks in most high performance digital systems such
as FIR filters, digital signal processors and microprocessors etc. Multiplication occurs frequently
in finite impulse response filters, fast Fourier transforms, convolution, and other important DSP
and multimedia kernels. The objective of a good multiplier is to provide a physically compact,
good speed and low power consuming chip. To save significant power consumption of a VLSI
design, it is a good direction to reduce its dynamic power that is the major part of total power
dissipation. In this thesis, we propose high speed low-power multiplier algorithms. The booth
multiplier will reduce the number of partial products generated by a factor of 2. The adder will
avoid the unwanted addition and thus minimize the switching power dissipation. The proposed
high speed low power multiplier can attain speed improvement and power reduction in the Booth
encoder when compared with the conventional array multipliers.
In this project, we propose high speed low-power multiplier algorithms. The booth multiplier will
reduce the number of partial products generated by a factor of 2. The adder will avoid the
unwanted addition and thus minimize the switching power dissipation. The proposed high speed
low power multiplier can attain speed improvement and power reduction in the Booth encoder
when compared with the conventional array multipliers. The power consumption concern and the
little occupancy are the major requirements of the fabrication of the DSP systems and other
efficient performing systems. The important criteria for improvement are the enhancing speed and
space of the multiplier. The speed and the space are relied on each other which mean increasing
speed concludes with the more consuming space. We have focused to come out with a conclusion
by studying more multipliers. We propose to study three different multipliers differently. This
thesis presents an efficient implementation of high speed multiplier using the array multiplier, shift
& add algorithm, Booth multiplier, pyramid algorithm & modify pyramid algorithm. In this thesis
we compare the working of these multipliers by implementing each of them separately.

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