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MIPS FSM Diagram!: Cycle 1!

This document presents a finite state machine diagram showing the steps in a MIPS processor's execution cycle. The diagram has multiple states including instruction fetch, instruction decode/register fetch, ALU operations, memory access, register write, and program counter write. Arrows show the transitions between each state over 5 clock cycles as the processor executes an instruction.

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SandipChowdhury
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61 views

MIPS FSM Diagram!: Cycle 1!

This document presents a finite state machine diagram showing the steps in a MIPS processor's execution cycle. The diagram has multiple states including instruction fetch, instruction decode/register fetch, ALU operations, memory access, register write, and program counter write. Arrows show the transitions between each state over 5 clock cycles as the processor executes an instruction.

Uploaded by

SandipChowdhury
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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MIPS FSM diagram

X.S. Hu 5-25
Finite State Diagram
t
i
P C W r i t e
P C S o u r c e = 1 0
A L U S r c A = 1
A L U S r c B = 0 0
A L U O p = 0 1
P C W r t e C o n d
P C S o u r c e = 0 1
A L U S r c A = 1
A L U S r c B = 0 0
A L U O p = 1 0
R e g D s t = 1
R e g W r i t e
M e m t o R e g = 0
M e m W r i t e
I o r D = 1
M e m R e a d
I o r D = 1
R e g D s t = 0
R e g W r i t e
M e m t o R e g = 1
A L U S r c A = 0
A L U S r c B = 1 1
A L U O p = 0 0
M e m R e a d
A L U S r c A = 0
I o r D = 0
I R W r i t e
A L U S r c B = 0 1
A L U O p = 0 0
P C W r t e
P C S o u r c e = 0 0
I n s t r u c t i o n f e t c h
I n s t r u c t i o n d e c o d e /
r e g i s t e r f e tc h
J u m p
c o m p l e t o n
B r a n c h
c o m p l e t i o n
E x e c u t o n
R - t y p e c o m p l e t o n
W r t e - b a c k s t e p
(
O

p

=

J

'
)

4
0
1
9 8
6
A L U S r c A = 1
A L U S r c B = 1 0
A L U O p = 0 0
M e m o r y a d d r e s s
c o m p u t a t i o n
M e m o r y
a c c e s s (
O

p
=
'
L
W

'
)

2
M e m o r y
a c c e s s
7
5 3
S t a r t
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
1

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