Digital Logic Design

Version 4.5 printed on June 2014

First published on August 2006
Digital Logic Design Page 2
Background and Acknowledgements

This material has been developed for the first course in Digital Logic Design. The content is derived from
the authors educational, technical and management experiences, in-addition to teaching experience.
Many other sources, including the following specific sources, have also informed by the content and
format of the following material:

Katz, R. Contemporary Logic Design. (2005) Pearson.
Wakerly, I. Digital Design. (2006) Prentice Hall.
Sandige, R. Digital Design Essentials. (2002) Prentice Hall.
Nilsson, J. Electrical Circuits. (2004) Pearson.

I would like to give special thanks to my students and colleagues for their valued contributions in making
this material a more effective learning tool.

I invite the reader to forward any corrections, additional topics, examples and problems to me for future

Thanks,
Izad Khormaee
www.EngrCS.com


































2014 Izad Khormaee, All Rights Reserved.
Digital Logic Design Page 3
Contents
Chapter 1. Number Systems, Number Representations, and Codes ................................................ 6
1.1. Key concepts and Overview ............................................................................................................. 6
1.2. Digital vs. Analog .............................................................................................................................. 7
1.3. Digital Design Overview (from Transistor to Super Computer) ........................................................ 9
1.4. Design Methodologies .................................................................................................................... 11
1.5. Number Systems (Decimal, Binary, Octal, Hexadecimal) .............................................................. 12
1.6. Base Conversions ........................................................................................................................... 14
1.7. Signed Binary Number Conventions .............................................................................................. 17
1.8. Binary Arithmetic ............................................................................................................................. 20
1.9. Binary Codes .................................................................................................................................. 22
1.10. DC Electrical Circuit Fundamentals .............................................................................................. 24
1.11. Additional Resources .................................................................................................................... 28
1.12. Problems ....................................................................................................................................... 29
Chapter 2. Boolean Algebra, Functions, and Minimization .............................................................. 30
2.1. Key concepts and Overview ........................................................................................................... 30
2.2. Logic Gates ..................................................................................................................................... 31
2.3. Huntingtons First Set of Postulates ............................................................................................... 34
2.4. Principle of Duality .......................................................................................................................... 35
2.5. Boolean Functions .......................................................................................................................... 36
2.6. Boolean Algebra Theorems ............................................................................................................ 38
2.7. Canonical or Standard Form of Functions ....................................................................................... 41
2.8. Methods of Function Minimization (reducing the number of literals in an expression)................... 46
2.9. Karnaugh-map or K-map ................................................................................................................ 48
2.10. Special Case: Dont Care Terms ................................................................................................ 52
2.11. XOR Properties and Applications ................................................................................................. 53
2.12. Additional Resources .................................................................................................................... 54
2.13. Problems ....................................................................................................................................... 55
Chapter 3. Analyzing and Synthesizing Combinational Logic Circuits .......................................... 56
3.1. Key concepts and Overview ........................................................................................................... 56
3.2. Standard Logic and Schematic Layout (Review)............................................................................ 57
3.3. Designing Logic Circuits ................................................................................................................. 62
3.4. Combinational Logic Analysis and Design ..................................................................................... 66
3.5. Compressing Truth Tables and K-maps ......................................................................................... 67
3.6. Glitches and Their Causes ............................................................................................................. 71
3.7. Types of Functions and Delays ...................................................................................................... 74
3.8. Beyond Standard Logic: Applications ............................................................................................. 76
3.9. Programmable Logic Devices (PLDs) ............................................................................................ 85
3.10. Additional Resources .................................................................................................................... 94
3.11. Problems ...................................................................................................................................... 95
Chapter 4. Introduction to Feedback Circuits and Sequential Logic Analysis ........................... 96
4.1. Key concepts and Overview ........................................................................................................... 96
4.2. SR Flip-Flops .................................................................................................................................. 97
4.3. Asynchronous Sequential Logic Issues .......................................................................................... 99
4.4. Finite State machine ..................................................................................................................... 101
4.5. Additional Flip Flops ..................................................................................................................... 107
4.6. Sequential Circuit Analysis ........................................................................................................... 112
4.7. Debouncing Mechanical Switches ................................................................................................ 118
Digital Logic Design Page 4
4.8. Additional Resources .................................................................................................................... 120
4.9. Problems ....................................................................................................................................... 121
Chapter 5. Sequential Circuit Design & Techniques .................................................................... 122
5.1. Key concepts and Overview ......................................................................................................... 122
5.2. Synchronous Finite State Machine Design (Classical Design) .................................................... 123
5.3. State Assignment Encoding, Shift Register Counters, and Adding an Enable Input ................... 133
5.4. Inspection Design Methods for Finite State Machines ................................................................. 137
5.6. FSM Design Examples ................................................................................................................. 143
5.7. Additional Resources .................................................................................................................... 151
5.8. Problems ....................................................................................................................................... 152
Chapter 6. Finite State Machine Optimization & Testing ............................................................ 153
6.1. Key concepts and Overview ......................................................................................................... 153
6.2. State Minimization and FSM Design Process .............................................................................. 154
6.3. State Minimization Using an Implication Chart (or Table) ............................................................ 155
6.4. Design for Testability (DFT) .......................................................................................................... 160
6.5. Additional Resources .................................................................................................................... 163
6.6. Problems ....................................................................................................................................... 164
Chapter 7 Verilog . Verilog Hardware Description Language (Verilog) ...................................... 165
7.1. Key concepts and Overview ......................................................................................................... 165
7.2. History ........................................................................................................................................... 166
7.3. Introduction to Verilog HDL ........................................................................................................... 167
7.4. Syntax ........................................................................................................................................... 169
7.5. Assignments ................................................................................................................................. 172
7.6. Operators ...................................................................................................................................... 176
7.7. Types and Variable Declarations .................................................................................................. 178
7.8. Flow Control Statements .............................................................................................................. 180
7.9. Code Modularization ..................................................................................................................... 182
7.10. Additional Resources .................................................................................................................. 183
7.11. Problems ..................................................................................................................................... 184
Chapter 8 VHDL . VHDL Hardware Description Language (VHDL) ............................................. 185
8.1. Key concepts and Overview ......................................................................................................... 185
8.2. History ........................................................................................................................................... 186
8.3. Steps in VHDL design ................................................................................................................... 187
8.4. Entity and Architecture .................................................................................................................. 189
8.5. Declarations .................................................................................................................................. 191
8.6. Operators ...................................................................................................................................... 198
8.7. Behavioral Design ......................................................................................................................... 200
8.8. Dataflow Design Elements ............................................................................................................ 202
8.9. Additional Resources .................................................................................................................... 206
8.10. Problems ..................................................................................................................................... 207
Chapter 9. Commercial Digital Integrated Circuits and Interface Design .................................. 209
9.1. Key concepts and Overview ......................................................................................................... 209
9.2. Output Types ................................................................................................................................ 210
9.3. Logic Families ............................................................................................................................... 214
9.4. Multiplexer (MUX)/DeMultiplexer (DMUX) Design ....................................................................... 215
9.5. Adder & Subtractor Design ........................................................................................................... 219
9.6. Multiplier Design ........................................................................................................................... 223
9.7. Arithmetic Logic Unit (ALU) Design .............................................................................................. 224
9.8. Additional Resources .................................................................................................................... 225
Digital Logic Design Page 5
9.9. Problems ....................................................................................................................................... 226
Appendix A. Additional Resources ................................................................................................... 227


Digital Logic Design Page 6
Chapter 1. Number Systems, Number Representations, and Codes

1.1. Key concepts and Overview

Digital vs. Analog
Digital Design Overview (from Transistor to Super Computer)
Design Methodologies
Number systems (Binary, Octal, Decimal, Hexadecimal)
Base Conversions
Signed Binary Number Conventions
Binary Arithmetic
Binary Code
DC Electrical Circuit Fundamentals
Additional Resources
Problems
Digital Logic Design Page 7
1.2. Digital vs. Analog
Natural forces and signals are all analog (or continuous) which means we hear, see and change items in
a continuous manner. On the other hand, our digital technology (also called non-continuous or 2-value
discrete) more effectively allows us to process and communicate more effectively. This leads us to
design systems that fit the following block diagram architecture:



Why convert analog data to digital data?
We have the information we need (on-off, timing)
Above a certain level is on, high, 1-state or true.
Below a certain level is off, low, 0-state or False.

Note: We have introduced a discontinuity when a signal goes from 1 to 0 or 0 to 1. This
means we cannot say what the exact value is at the time of transition.

Reduces complexity of signals and the solutions to work with the signal.
To deal with a digital signal we need to deal with binary algebra.
To deal with an analog signal we need to deal with calculus to approximate.

Positive vs. Negative logic
Positive Logic Convention (Default easier for humans to understand)
- H, (V > Vmax) is 1-state or True
- L, (V < Vmin) is 0-state or False
Negative Logic Convention (1 is L and 0 is H)
- H, (V > Vmax) is 0-state or False
- L, (V < Vmin) is 1-state or True


Real World
Signal
Analog to
Digital
Convertor
Process/
Store/
Communicate
Digital to
Analog
Convertor
Real World
Signal
Example: Music Microphone Memory Chip Speaker Music
Digital Logic Design Page 8
Example of analog and digital representations of human Heart Beat:

Based on the definition of a digital (2-valued) system, what are some examples where a digital
system could apply? What are the variables and on/off or high/low states?

Example: Describe the input and output of a traffic intersection in digital form.
Solution:
Cars presence at an intersection:
(Car PresentMagnitude is 1, No Car PresentMagnitude is 0)

Status of Traffic Lights:
(Red-on 1, Red-off 0)

Extension: draw a typical Intersection and label the output and input in digital form.

t
V
Vmax
Vmin
H (>Vmax)
L (<Vmin)
V
t
Analog to
Digital
Converter
(ADC)
Digital to
Analog
Converter
(DAC)
Digital
Analog
Digital Logic Design Page 9
1.3. Digital Design Overview (from Transistor to Super Computer)
All digital systems from the smallest to largest run on a 2-valued system (also called Binary system).
So a mechanism is needed to represent the two values. This is typically accomplished with a switch
that can be on or off. In the early days, mechanical switches were used, followed by vacuum tubes
as switches. Today we use transistors that can be configured to approximate the switch on and off
modes. Transistors are fast, inexpensive and small.


Transistor overview (the invention that makes todays automation possible)
The transistor, invented by three scientists at the Bell Laboratories in 1947, rapidly replaced the
vacuum tube as an electronic signal regulator.

Transistors are the basic elements in integrated circuits (ICs). An IC consists of a very large
number of transistors interconnected with circuitry and packaged into a single silicon microchip or
"chip." A typical processor chip has many millions of transistors.

A transistor is developed based on semiconductor material characteristic. Semiconductor
material used basically as a switch as shown below:



Semiconductor material is given special properties by a chemical process called doping. The
doping results in a material that either adds extra electrons to the material (which is then called N-
type for the extra negative charge carriers) or creates "holes" in the material's crystal structure
(which is then called P-type because it results in more positive charge carriers).

Today's computers use circuitry made with complementary metal oxide semiconductor (CMOS)
technology. CMOS uses two complementary transistors per gate (one with N-type material; the
other with P-type material). When one transistor is maintaining a logic state, it requires almost no
power when not switching.


Semiconductor Integration scaling

Small-Scale Integration, SSI (Basic gates: OR, NOR, NOT, AND)

Example: Inverter (NOT) is a common SSI element used in Digital Design (Vendors provide
usage information and specifications in the form of a data sheet)
Base
Emitter (E)
Collector (C)
NPN Transistor Example
A small current at the base causes the CE connection to change from open to a short
P-Type
N-Type
Base
Collector
N-Type
Emitter
Digital Logic Design Page 10



Medium Scale Integration, MSI
PAL--Programmable Array Logic, GAL--Generic Array Logic, EPROM--Erasable
Programmable Read Only Memory, ADDER, COUNTER)
- 1,000s to 100,000s of gates.
- Typically, the vendor provides information in the form of a data sheet

Large Scale Integration (LSI)
- 100,000s to Millions of gates
- Typically implements complex functionality
- Processors such as special function controllers and interface chips

Very Large Scale Integration (VLSI)
- Millions to Billions of gates
- Typically includes extensive functionality
- Processors such as Intels Pentium are examples of VLSI.

Design / Analysis tools
- We will be using manual processes for most of this text to design/analyze digital circuits
in order to gain in-depth understanding of logic design.
- The final section of this text is dedicated to the use of Hardware Description Language
(HDL) to automate design, simulation, implementation, and analysis and verification
process.

1. Block Diagram
A B
Input Output
A B
0
1
1
0
2. Truth Table
A

B

t
Propagation Delay
3. Timing Diagram
A
B
4. Equivalent Circuit
+5 V
GND
Digital Logic Design Page 11
1.4. Design Methodologies
Digital design depends on the type of problem, the work already completed, the strategic direction of the
organization and the skills/resources available to the project team. Having said that, in general, there are
three approaches available to the designers under traditional Hierarchical-Oriented Designs:
Top-down Design Methodology
Start with larger block of design and then work out the detail of each block.

Bottom-up Design Methodology
Start with components and figure out how to interconnect them to design the system.

Middle-out Design Methodology
A combination of the bottom-up and top-down. Most designs are done this way: start with the
top-down design, then modify the design to take advantage of the available components (based
on cost, availability, and reliability).

Another way of thinking about the problem of design that has a strong following in the software
development community and is being used in the hardware community under the module design concept
is Object-Oriented Design (OOD).

Designers commonly agree that there are four main properties or benefits associated with object-oriented
design:
Encapsulation
As the name implies, the internals of the design are hidden from the user and only the interface
definition (input/output) are available to the user. Users benefit since they have a limited amount
of information to learn. Designers benefit since they are able to upgrade the module without
involving the user as long as the new interface is a superset of an existing interface.

Inheritance
This simply means that an object may be built on the features available in the base object
property. Of course, the benefit is that the designers only have to work on the additional feature
and simply reuse the existing functionality.

Polymorphism
OOD allows the designer to create objects that behave differently based on the attributes of input.

Composition (One object can be built using many others.)
A new object may be developed based on the composition of multiple existing objects.

Hopefully, at this point you are thinking why wouldnt everyone use OOD? The main drawback of
OOD is the high level of planning required for each module, and discipline needed to follow the four
properties in design.
Digital Logic Design Page 12
1.5. Number Systems (Decimal, Binary, Octal, Hexadecimal)
We have learned and use the decimal numbering system simply because humans are born with ten
fingers! The decimal system has served us well. But with digital systems, we need a 2-value system
(binary). We could attribute this to the fact that computers only have open or closed switches (or one
finger, if you prefer).

This means, we have to learn the binary system in addition to the decimal system. We also will discuss
the octal and hexadecimal systems because conversion to/from binary is easy and numbers in these
systems are easier to read than binary numbers for humans.
Decimal Number (base or radix 10)
Humans use the decimal numbering system as a default, so when you see a number 56 your
assumption is that its base or radix is 10 or (56)
10
which is 56 base 10.

Each digit is weighted based on its position in the sequence (power of 10) from the Least
Significant Digit (LSD, power of 0) to the Most Significant Digit (MSD, highest power).

Each digit must be less than 10 (0 to 9)

For example (2375.46)
10
is evaluated as:

MSD LSD
Digit notation d
3
d
2
d
1
d
0
. d
-1
d
-2

Digit 2 3 7 5 . 4 6
Value 10
3
10
2
10
1
10
0
10
-1
10
-2

Results=Value*Digit 2000 300 70 5 0.4 0.06


(2375.46)
10
= 2x10
3
+ 3x10
2
+ 7x10
1
+ 5x10
0
+ 4x10
-1
+ 6 x10
-2

= 2000 + 300 + 70 + 5 + 0.4 + 0.06
Note: The general term for decimal point is radix point.

Binary Number (base or radix 2)
Digital and computer technology is based on the binary number system, since the foundation is
based on a transistor, which only has two states: on or off.

Each digit of the number is called a bit or which is a short for binary digits
An 8-bit group is referred to as a Byte
An 4-bit group is referred to as a nibble

Each bit is weighted based on its position in the sequence (powers of 2) from the Least
Significant Bit (LSB) to the Most Significant Bit (MSB).

Each bit must be less than 2 which means it has to be either 0 or 1.

For example (1010.11)
2
is evaluated as:

MSB LSB
Digit notation b
3
b
2
b
1
b
0
b
-1
b
-2

Digit 1 0 1 0 1 1
Value 2
3
2
2
2
1
2
0
2
-1
2
-2

Results=Value*Digit 8 0 2 0 0.5 0.25

Digital Logic Design Page 13
(1010.11)
2
= 8 + 0 + 2 + 0 + 0.5 + 0.25 = (10.75)
10

Note: The general term for decimal point is radix point

In binary, the count starts at 0 (called 0-referencing), where in decimal, the count typically starts
with 1 (called 1-referencing)

Octal (base 8) and Hexadecimal (base 16)
These number systems are used by humans as a representation of long strings of bits since they are:

Easier to read and write, for example (347)
8
is easier to read and write than (011100111)
2
.

Easy to convert (Groups of 3 or 4)

Today, the most common way is to use Hex to write the binary equivalent; two hexadecimal digits
make a Byte (groups of 8-bit), which are basic blocks of data in Computers.

Question: The hexadecimal system is base 16, so the digits range in value from 0 to 15. How do you
represent Hexadecimal digits above 9?

Use A for 10, B for 11, C for 12, D for 13, E for 14 and F for 15. So (CAB)
16
or (CAB)
HEX
is a valid
hexadecimal number.

Computer memory is typically organized in 8-bit groups or bytes. Why groups of 8?

Digital Logic Design Page 14
1.6. Base Conversions
Decimal to Binary Conversion
Alternative 1 Subtract the weight method
Steps:
+ Find the largest power of 2 (2
n
) that can be subtracted out of the decimal number
+ Take the result and subtract (2
n-1
) from it
If the result is not negative then that bit is one
If the result is negative, then that bit is zero and the result equals the result from
step 1
+ Repeat step 2 until the result is exactly 0

Example: convert (49)
10
to a binary number


Alternative 2 Division by 2 method
Steps:
+ Divide the decimal number by 2
Remainder is the least significant bit (most right bit)
Quotient is used in the next step
+ Divide quotient by 2
Remainder is the next significant bit (next left bit)
Quotient is used in the next step
+ Repeat previous step until quotient is 0

Example: convert (49)
10
to a binary number


Binary to Decimal Conversion Add the weight method
Step:
Simply multiply each bit with its weight and add to get the decimal number

Example: Convert (110001)
2
to a decimal number
(110001)
2
= ( 1* 2
5
+ 1* 2
4
+ 0* 2
3
+ 0* 2
2
+ 0* 2
1
+ 1* 2
0
)
10
= (49)
10

Binary Octal Conversion - Group of 3 method
Remainder
2|49 1 (LSB)
2|24 0
2|12 0
2| 6 0
2| 3 1
2| 1 1 (MSB)
2| 0 Stop
(49)
10
(110001)
2

49
-32
----
17

2
n


Results
17
-16
----
1
Binary # ( 1 1 0 0 0 1)
2

1
-8
----
-7
1
-4
----
-3
1
-2
----
-1
1
-1
----
0
When =0, done
>0
Digital Logic Design Page 15
Step:
(1) Each three bits in binary (right to left) equals one octal digit in the same direction)

Example - Convert (10110111)
2
to an Octal number.

Reverse the process to convert from Octal to Binary

Binary Hexadecimal Conversion - Group of 4 method
Steps:
(1) Each four bits in binary (right to left) equals one hex digit in the same direction)

Example:- Convert (110110111)
2
to a hexadecimal number


Reverse the process to convert from hexadecimal to binary


Any base to Decimal Conversion - Polynomial Function Method
The most general number in any base is the real number and the general rule is as follows:

(Real Number)
r
= (d
j
d
1
d
0
. d-
1
d
-2
)
r
= (d
j
r
j
+ +d
1
r
1
+ d
0
r
0
+ d
-1
r
-1
+ d
-2
r
-2
+ )
10


Example The most common conversion is Hex integer to decimal base. For this example,
convert (1CAB)
16
to decimal:

(1CAB)
16
= (1*16
3
+ 12*16
2
+ 10*16
1
+ 11*16
0
) = (7339)
10

Example - Although not common, lets do an example of converting a real binary number to
decimal so Convert (11010)
2
to decimal.

(11010.11)
2
= ( 1*2
4
+ 1*2
3
+ 0*2
2
+ 1*2
1
+ 0*2
0
+ 1*2
-1
+ 1*2
-2
) = (26.75)
10


Integer Decimal Conversion to any Base Repeated Radix Division Method
The solution is based on the fact that
(integer number)
10
= d
n
r
n
+ + d
2
r
2
+ d
1
r
1
+ d
0
r
0
= (d
n
d
2
d
1
d
0
)
r


Steps:
(1) If (integer number)
10
is divided by r, the remainder is d
0
(Least Significant Digit, LSD)
(2) If the quotient from step 1 is divided by r the remainder is the next digit
(3) Repeat step 2 until the quotient is zero were the remainder is the d
n
(Most Significant
digit, MSD)


( 0001 1011 0111 )
2

( 1 B 7 )
16

( 010 110 111 )
2

( 2 6 7 )
8

0 is added to
make a group of 3
Digital Logic Design Page 16

Example: Convert (52)
10
to binary (radix, r = 2)


Therefore (52)
10
= (110100)
2



Decimal Fraction Conversion to any Base Repeated Radix Multiplication Method

Solution is based on the approach:
(decimal fraction)
10
= d
-1
r
--1
+ d
-2
r
--2
+ = (.d
n
d
2
d
1
d
0
)
r
r*(decimal fraction)
10
= d
-1
+ d
-2
r
-1
+ = (.d
-1
d
-2
d
-3
)
r


Steps:
(1) Multiply (fraction)
10
by r, the non-fractional part is the first digit
(2) Continue step 2 until fraction is 0

Example: Convert (.125)
10
to binary (r=2)

Solution:

Therefore (.125)
10
= (.001)
2


Note: Some numbers may not be fully convertible, so you have to decide the number of decimal
points you need to convert. For example (1/12)
10
does not fully convert to binary number.

.125
x 2
-----
0.25
d
-1

.25
x 2
-----
0.5
d
-2

.5
x 2
-----
1.0
d
-3

Fraction is 0 which means d
-3
is the Least Significant Digit
Non-fraction portion is 1 which means d
-3
is 1.
Non-fraction portion is 0 which means d
-1
,the Most Significant Digit, is 0.
52
-4
----
12
-12
----
0
26
2
13
2
13
-12
------
1
6
2
6
-6
----
0
3
2
Remainders
R
0
=d
0
=0 R
1
=d
1
=0 R
2
=d
2
=1 R
3
=d
3
=0 R
4
=d
4
=1 R
5
=d
5
=1
26
-2
----
06
- 6
----
0
3
-2
----
1
1
2
1
0
----
1
0
2
Quotient is 0 therefore remainder is MSB
First Remainder is the LSB
Digital Logic Design Page 17
1.7. Signed Binary Number Conventions
Signed Binary Number Representations (3 methods)

Signed Magnitude (SM)
Easiest for people to read (Not used by computers)
Here is an example of Signed Magnitude number with 4-bit word size


Binary SM numbers for n-bit word ranges from +(2
n-1
1) to -(2
n-1
1)
Note: there are two values for zero (Sign-bit = 1 and Sign-bit=0)

Example of complete list of binary SM numbers for a 4-bit word.

Binary SM Number (n=4) Decimal Number
d3 d2 d1 d0
0 1 1 1 + 7 = +(2
4 -1
-1)
0 1 1 0 + 6
0 1 0 1 + 5
0 1 0 0 + 4
0 0 1 1 + 3
0 0 1 0 + 2
0 0 0 1 + 1
0 0 0 0 + 0
1 0 0 0 - 0
1 0 0 1 - 1
1 0 1 0 - 2
1 0 1 1 - 3
1 1 0 0 - 4
1 1 0 1 - 5
1 1 1 0 - 6
1 1 1 1 - 7 = -(2
4 -1
-1)


Diminished Radix Complement (DRC) or 1s complement
Some computer systems use this information because it is easier to convert.

To obtain a negative DRC or 1s complement:
Write a positive number with MSB set to 0 (positive sign)
Negate (Invert) every bit including sign bit to obtain the negative number.

(+5)
10
= (0 1 0 1 )
2SM
( -5)
10
= (1 1 0 1)
2SM

One Sign Bit
0 +
1 -
3 Magnitude Bit
Digital Logic Design Page 18
Here is an example of 4-bit word size:


DRC numbers for n-bit word ranges from +(2
n-1
1) to (2
n-1
1)
Note that there are two values for zero (Sign-bit = 1 and Sign-bit=0)

Example of Binary DRC or 1
s
Complement Numbers for a 4-bit word

Binary SM Number (n=4) Decimal Number
d3 D2 d1 d0
0 1 1 1 + 7 = +(2
4 -1
-1)
0 1 1 0 + 6
0 1 0 1 + 5
0 1 0 0 + 4
0 0 1 1 + 3
0 0 1 0 + 2
0 0 0 1 + 1
0 0 0 0 + 0
1 1 1 1 - 0
1 1 1 0 - 1
1 1 0 1 - 2
1 1 0 0 - 3
1 0 1 1 - 4
1 0 1 0 - 5
1 0 0 1 - 6
1 0 0 0 - 7 = -(2
4 -1
-1)


Radix Complement (RC) or 2s complement
Majority of Digital Systems use RC since it simplifies the binary arithmetic operation.

To obtain a negative RC or 2s complement:
Write a positive number with the MSB set to 0 (positive sign)
Negate (Invert) every bit including sign bit
Add a 1 to the result to obtain the negative number

Note: Taking the 2s complement of the result will return the original positive number.

Below is an example of 4-bit number of SM to RC:

(+5)
10
= (0 1 0 1 )
2DRC
( -5)
10
= (1 0 1 0)
2DRC

One Sign Bit
0 +
1 -
3 Magnitude Bit
Digital Logic Design Page 19


RC numbers for n-bit word range from +(2
n-1
1) to (2
n-1
) with the following two characteristics:
The range is not symmetrical, there is one more negative number than there are positive
numbers.
There is only one pattern for zero (-0 and +0 have the same pattern)

Example of Binary RC or 2s Complement Numbers for a 4-bit word

Binary SM Number (n=4) Decimal Number
d3 d2 d1 d0
0 1 1 1 + 7 = +(2
4 -1
-1)
0 1 1 0 + 6
0 1 0 1 + 5
0 1 0 0 + 4
0 0 1 1 + 3
0 0 1 0 + 2
0 0 0 1 + 1
0 0 0 0 + 0
0 0 0 0 - 0
1 1 1 1 - 1
1 1 1 0 - 2
1 1 0 1 - 3
1 1 0 0 - 4
1 0 1 1 - 5
1 0 1 0 - 6
1 0 0 1 - 7
1 0 0 0 -8 == -2
4 -1


Quick Inspection Method Finding 2s complement
Working from the LSB of the number to be complemented toward the MSB (right to left),
rewrite each bit up to and including the first 1 encountered, then complement each bit
thereafter
Example:
MSB LSB
Old Number: (1 0 1 1 0 1 0)
2s Complement: (0 1 0 0 1 1 0)

**Note: 2s complement gets you back to the original number.
(+5)
10
= (0 1 0 1 )
2RC

( -5)
10
= -(0 1 0 1)
2RC


Bit-invert 1 0 1 0
Add 1 + 1
-----------
2s Compl. (1 0 1 1)
2RC

One Sign Bit
0 +
1 -
3 Magnitude Bit
Digital Logic Design Page 20
1.8. Binary Arithmetic
All of todays computer systems use RC numbers (2s complement) for binary arithmetic operations. The
reset of this section provides description of Binary Arithmetic using RC numbers.

Addition of Signed Binary Numbers
When adding RC numbers, simply add then ignore the left-most carry.

+7 0 1 1 1
+(-2) 1 1 1 0
----------
0 1 0 1 Ignore the left-most carry, and the result is +5

Notes:
- The left-most bit is a sign bit and there are three magnitude bits.
- As long as we know results fits within the 1 sign-bit and n magnitude bits, this process
works. Otherwise we need to consider the overflow.

Addition of Unsigned Binary Numbers
Unsigned addition Signed works exactly the same way as singed addition, allowing us to use the
same circuitry.

+7 0 1 1 1
+3 0 0 1 1
----------
1 0 1 0 Result is +10. If there is a carry beyond the available bits, then an
an overflow has occurred.

Overflow
An overflow occurs when the addition of two numbers results in a number larger than can be
expressed with the available number of bits.

Example performing the operation, 8+9=17; in a 4-bit word system, results in an overflow
since 4 bits can only store 0 to 15. The result will show as a 1, which is 16 less than the
correct result.

Detecting overflow
Unsigned number addition
If the addition has a carry beyond the available bits then an overflow has occurred.

Signed (RC, 2s complement) number addition
- If the operands have different signs, then overflow cannot occur, since one number is
being subtracted from the other.
- If the operands have the same sign and the result has a different sign, then an overflow
has occurred.
A quick way to identify an overflow situation is when the carry into the sign-bit position
and the carry out of sign-bit position are different. Example
Digital Logic Design Page 21


Subtraction (indirect method)
If you write subtraction as addition with a negative number, then the previous method can be used.

For example:
{2 6} can be done by performing {2 + (-6)}

-5 1 0 1 1
+(-6) 1 0 1 0
----------
0 1 0 1 Result is +5 which is wrong
since -5 +(-6) = -11
1 0 1 0 Carry bits
The sign is 0 (+) where
the two operands had sign
1 (-), indicating an
overflow.
The carries in and out of sign-
bit are different, indicating an
overflow.
Digital Logic Design Page 22
1.9. Binary Codes

Binary codes are used to translate human symbols to one and zeros. The most important of the symbols
is the alphabet used for human communications. So every key and character has to have a unique
binary code. The minimum number of bits required to uniquely identify all the keys on the keyboard must
meet the following condition:

2
Number of Bits
Number of keys

ASCII Code
Initially, IBMs scheme of representing alphanumeric and control characters for computers was the
most commonly used coding method. The coding scheme was referred to as the Extended Binary-
Coded Decimal Interchange Code (EBCDIC). Its dominance was driven by IBMs near-monopoly
position in the computer industry until the early 1980s.

The majority of other manufacturers were looking for a non-proprietary coding, leading to the
American Standard Code for Information Interchange (ASCII) coding. ASCII was adopted by the
majority of vendors and very quickly overtook EBCDIC as the most commonly used coding scheme.

ASCII code is used to represent alphanumeric and control characters with 8 bits. The ASCII code
table is shown below:



In early 1990, the need for a code that was capable of representing Asian languages with large
Digital Logic Design Page 23
number of characters became an important competitive question. Up to that point, the language of
computer interfacing was English and to lesser extend other western languages that have less than
256 characters. The ASCII code could represent them using its 8-bit word with 256 unique codes.
But this is not true for a number of Asian languages.

In order to meet the need for the larger Asian languages character set and maintain compatibility
with ASCII code, Unicode was introduced. Unicode use 16 bits, so it is capable of representing as
many as 2
16
or 65,536 unique symbols. The majority of todays computers use Unicode which is also
referred to as the double byte code.

Other Binary Codes

Binary coded decimal (BCD)
BCD assigns 4 binary bits to each binary digit. The only drawback is that only 0 to 9 are used,
and the other 6 combinations from 10 to 15 are not used.

Reflective Gray Code (RGC)
RGC is a binary number system organized so that consecutive codes in the sequence only
require one bit change as shown below:


2-bit Reflective Gray Code
00
01
11
10
3-bit Reflective Gray Code
000
001
011
010
110
111
101
100
Binary Coded Decimal
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9

Digital Logic Design Page 24
1.10. DC Electrical Circuit Fundamentals

The basic components used here are resistors and power supplies. The power supply provides energy to
the circuit and the simplest power supply is a battery. Resistors are material that limit the amount of
current follow.

This section discusses the generation and sensing of logic 1 which is typically equal to 3.5 and 5 volts.
On the other hand, logic 0 is typically less than 0.7 volts.

Electrical Resistance
Resistor Symbol

Resistance is the capacity of a material to impede the flow of current (electric charge). The
most common use of resistors is to limit current flow.

The flow of current through a resistor will convert electrical energy to thermal energy.
In some applications, this property is desirable and in other application it is undesirable. Here
are examples of each:

- Undesirable: transmission line, digital devices
- Desirable: heater, toaster. oven, stove top

Resistance, R, is a basic ideal element so it is defined in term of current, I, and Voltage.
Ohms law: V = I * R where:
- R value is in Ohms or O
- V is in volts
- I is in Amperes

Power
Power is measured in Watts and can be calculated using the following equations.
P= V
2
/R = I
2
*R where
V is the voltage and is in volts
I is the current in Amps
R is the resistance in Ohms

Example
Find the value of the resistance ,R, and the power consumed by the resistor if Vg = 1 kV and Ig =
5 mA.
R
+ - V
I
Digital Logic Design Page 25


Solution
- R= Vg/Ig = 1000/0.005 = 200 k
P
r
= I
g
2
* R = (.005)
2
*(200,000)= 5 W


Circuit simplification by combining resistors
Resistors in Series
Resistors in series can be replaced by an equivalent resistor that is the sum of all the
resistors in series.

Resistors in Parallel
Resistors in parallel can be replaced by an equivalent resistor as shown below:

Example
Find values of I
1
and I
2
for the following circuit:

Solution:
1) Simplify the circuit by combining the two 1 MO parallel resistors with the 1 kO resistor that is in
1 kO
1 MO
+

+5V

-
I
1

I
2

1 kO
1 MO
R
1
R
2

R
n

1/R
eq
= 1/R
1
+ 1/R
2
+ + 1/R
n

. . .
R
1
R
2
R
n

. . .
R
eq
= R
1
+ R
2
+ + R
n

+
-
V
g

R
I
g

Digital Logic Design Page 26
series with them.

2) Redraw the circuit and apply Ohms law (V=I*R) to find currents.

I
1
= V / R = 5 / 1000 = 0.005 A = 5 mA
I
2
= V / R = 5 / 501000 = 0.00001 A = 10 uA

Note: The amount of current through each resistor is inversely proportional to the size of the
resistors.

Using a switch to create logic 1 +5 v and logic 0 Ground or 0 v



1 kO
Switch
+

+5V

-
Output:
1 when switch is open
0 when switch is closed
Typically
drawn as
1 kO
Vcc
Gnd
Output
1 kO
+

+5V

-
I
1

I
2

501 kO
1 kO
1 MO
+

+5V

-
I
1

I
2

1 kO
1 MO
1/R
1
= 1/10
6
+ 1/10
6
= 2/10
6
R
1
= 500 kO
R
2
= 500 + 1 = 501 kO
Digital Logic Design Page 27
What is the voltage at the output (vo) when the switch is Opened and closed in the following
circuit:

Solution:




1 kO
Vcc
Gnd
Output,
Vo
1 MO
Switch Open
I
I
1 kO
Vcc
Gnd
Output,
Vo
1 MO
Switch Closed
I
I
2
= 0
I = V/R = 5 / (1001 x 10
3
)
I ~ 5 x 10
-6
A
Vo = 0 + 10
6
x5 x 10
-6 =
= 5v
Vo=0
The output is directly Connected to
Ground or 0 v
1 kO
Vcc
Gnd
Output
1 MO
Digital Logic Design Page 28
1.11. Additional Resources

Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 1 & 2. introduction & Number Systems and Code
Digital Logic Design Page 29
1.12. Problems
Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.

Digital Logic Design Page 30
Chapter 2. Boolean Algebra, Functions, and Minimization

2.1. Key concepts and Overview

Logic Gates
Huntingtons First Set of Postulates
Principle of Duality
Boolean Functions
Boolean Algebra Theorems
Canonical or Standard Forms (Min-term and Max-term)
Function Minimization
Karnaugh Maps (K-Maps)
Special Case: Dont Care Terms
Exclusive OR Properties and Applications
Additional Resources
Problems
Digital Logic Design Page 31
2.2. Logic Gates
The rest of the class relies on two-valued Boolean Algebra, i.e. B = {0, 1}
We use variables X, Y, Z, A, B, and constants 0 and 1
**Note 0 and 1 are also called identity elements

Binary operators
+ called OR
- OR symbol Z=X+Y

- OR truth table
X Y X+Y
0 0 0
0 1 1
1 0 1
1 1 1

- Review the 74LS32 Data sheet on the website

. called AND
- AND symbol Z=X.Y

- AND truth table

X Y X.Y
0 0 0
0 1 0
1 0 0
1 1 1

- Review the 74LS08 Data sheet on the website

Called NOT, Inversion, negation
X
Y
Z
X
Y
Z
Digital Logic Design Page 32
- NOT symbol Z= X =X (Also called the complement)

- NOT truth table
X Z=X
0 1
1 0

- Review the 74LS04 Data sheet on the website

Order of Operation Precedence (Same as decimal arithmetic)
Highest to lowest order of Precedence for Binary Operator: =, (), , ., +
Note:
Parentheses are used to force the operation order sequence much like decimal Algebra.
The equal sign = is same as decimal algebra for assignment.

An expression is a combination of variables and binary operators Z+ XY + X

The number of Literal is the total occurrences of all variables in an expression.
For example f(x,y,z) = x+ y.x.z + x.y.z is said to have 7 literals. The number of literals typically
used as a measure of implementation complexity.

Additional standard logic gates:

NOR is an OR gate with the output negated
Review the 74LS02 Data sheet on the website

NAND is an AND gate with the output negated
Review the 74LS00 Data sheet on the website

XOR (also called Module 2 add or exclusive or) Y X Y X Y X . . + =
XOR Symbol

XOR Truth Table
Review the 74LS86 Data sheet on the website

X Y
Y X
0 0 0
0 1 1
1 0 1
1 1 0
X
Y
Z
X Z
Digital Logic Design Page 33

When using three variables, the operation is performed on two at a time as shown below:
Z Y X Z Y X = ) (
XOR is commonly used to check if there is an odd or even number of 1s. This check is
called parity. Odd parity is when there are odd numbers of 1s and even parity is when
there are an even number of 1s. Parity check is used for single bit error detection.

XNOR (also called equality coincidence or exclusive nor) Y X Y X Y X . . . + = .
XNOR Truth Table

X Y
Y X
0 0 1
0 1 0
1 0 0
1 1 1

When using three variables, operation is perform on two at a time as shown below:
Z Y X Z Y X = ) (
XNOR is not commonly available as a standard stand alone chip.

Digital Logic Design Page 34
2.3. Huntingtons First Set of Postulates
Postulates, Axioms or propositions are self-evident mathematical statements that are stated without
proof. The following Postulates will be used to develop Boolean Algebra.

P1a: If X and Y are in B, then X+Y is in B
P1b: If X and Y are in B, then XY is in B

P2a: There is an element 0 such that X+0 = X for every variable X.
P2b: There is an element 1 such that X1=X for every variable X.

P3a: X+Y = Y+X (Commutative with respect to +)
P3b: XY = YX (Commutative with respect to .)

P4a: X+YZ = (X+Y)(X+Z) (+ is distributive over .)
P4b: X(Y+Z)=XY+XZ (. is distributive over +)

P5: For every variable X, there is a variable X such that
a: X + X = 1
b: X X = 0

P6: There are at least two distinct elements in B.

Digital Logic Design Page 35
2.4. Principle of Duality
Dual of an expression is obtained by:
Interchanging 0 and 1
Interchanging . and +

(Exp)
D
represent dual of (Exp) examples:
(X+0)
D
= X.1
(X + Y.Z)
D
= X.(Y+Z) **Note: it is not equal to X.Y + Z

You may recognize that Huntingtons first set of Postulates are true for duals (a and b of each
postulate)

Digital Logic Design Page 36
2.5. Boolean Functions
Pure form
X.Y.Z is called the product of terms when literals are ANDed together
X+Y+Z is called the sum of terms when literals are ORed together

Mixed forms
(X+Y).(Z+Y+X) this form is called the product of sums form (POS form)
X.Y + Y.Z this form is called the sum of products form (SOP form)

Truth table for a function

Steps
Identify all possible combination of 1s and 0s. For an n variable function, there will 2
n

rows in the table counting from 0 to 2
(n-1)
.
Evaluate the output function value for each set of input variable values.

Example
Draw a system diagram and generate a truth table for the function, F(X, Y, Z) = X.Y + Y.Z + Z.Y

System Diagram



Truth Table
X Y Z F(X,Y,Z)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
0
1
1
0
0
1
1


System
F(X, Y, Z)
Output Input
X
Y
Z
Digital Logic Design Page 37
Example Basics of Digital Logic
Develop a system diagram and truth table for two gates that ensure only one fish leaves the
Outer Door at any one time. Below is the physical diagram of the system:



Aquarium
Outer Door
Inner Door
Holding Area
- Holding Area has a sensor with 2 bit output
( 00: empty, 01:one fish, 10 & 11: more than one fish)
- Each door has one input where logic 1 opens and logic 0 closes the door.
Digital Logic Design Page 38
2.6. Boolean Algebra Theorems
Purpose of Theorems
The Theorems & Huntingtons Postulates are key in our ability to reduce the number of literal
(variables) used in a function and therefore reduce the number of gates required to implement a given
function. Sometimes they are used to simply rearrange the expression so it is easier to implement.

Example: (X+Y)(X+Y )=X
It is clear that right-hand-side requires fewer gates to implement compared to the left hand side.

Two methods available for proving theorems
Prove through Boolean Algebra
Use the Huntingtons postulates or theorems already proved to show that both sides of theorem
are the same.

Prove through Truth Tables
Show that for all possible values on the left hand-side is equal to the right-hand side of the
equation. This method works well for a small number of variables.

Theorems and proofs
Theorem 1 Double Complementation or Double Negation Theorem
a) X X =

Theorem 2 Idempotency Theorem
a) X+X = X
b) XX = X

Theorem 3 Identity Element Theorem
a) X + 1 = 1
b) X0 = 0

Theorem 4 Absorption Theorem
a) X + XY=X
b) X(X+Y) = X

Theorem 5 Associative Theorem
a) X + (Y+Z) = (X + Y) + Z
b) X(YZ) = (XY)Z

Theorem 6 Adjacency Theorem
a) XY + X Y = X
b) (X + Y)(X + Y ) = X

Theorem 7 Consensus Theorem
a) XY + X Z + YZ = XY + X Z
b) (X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z)

Theorem 8 Simplification Theorem
a) X + X Y = X + Y
b) X( X + Y) = XY

Digital Logic Design Page 39
Theorem 9 DeMorgans Theorem (2-Variable form)
a) Y X Y X . = +
b) Y X Y X + = -

Theorem 10 DeMorgans Theorem (General form)
a)
n n
X X X X X X - - - = + + +
2 1 2 1

b)
n n
X X X X X X + + + = - - - . .
2 1 2 1


Example of two type of Proofs (Truth Table and Algebraic)
Prove Theorem 8, Simplification Theorem.
Hint: Use truth table

Prove Theorem 10, DeMorgans Theorem (General form).
Hint: Apply Theorem 9.

Utilizing Demorgans Theorem NAND and NOR gates may be represented using the others base
signal as shown below (not circle indicates complement):

Transforming from one form to another requires only two steps:

1) Complement every input and output.
2) Swap OR and AND gates.

Example: Design an XOR using only NAND gates.
F(A,B) = A B

Solution:
F(A,B) = A.B + B.A
Apply conversion rules Complement every input and output; Swap ORs and ANDs
F(A,B) = ((A.B) . (B.A))

Gate Type
NAND gate



NOR gate



AND gate


OR gate
AND form OR form
=



=


=


=
Digital Logic Design Page 40


B
F(A,B)
A
Digital Logic Design Page 41
2.7. Canonical or Standard Form of Functions
Typically, a function has to be written in one of the two standard forms before the minimization step.
The two standard forms are:

Standard Sum of Products (SOP)
Standard Product of Sums (POS)

Obtaining Standard Sum of Products (SOP) Forms of Functions
In standard or canonical SOP form, all the variables are present in each product term.

Example - for f(A,B) = A+B

1) System Diagram



2) Write the Truth table to see all the possible value of F(A,B)

Input Output
A B F(A,B)=A+B
0 0 0
0 1 1
1 0 1
1 1 1

3) Write the full product term for all the possible combinations

F(A,B) = F(0,0). B A. + F(0,1). B A + F(1,0). B A. + F(1,1). B A.
F(A,B) = 0. B A. + 1. B A + 1. B A. + 1. B A.

F(A,B) = 1. B A + 1. B A. + 1. B A. Canonical or Standard Form

A standard product or min-term is a product of all independent input variables for a function that
corresponds to a row of the truth table with output of 1. For example, B A. is a min term in the
above example.


System
A
B
F(A,B) = A + B
Digital Logic Design Page 42
Lets take another example from problem statement to truth table to min-terms and the resulting
sum of products.

Step 1) Understand the problem
Write out an expression for the function that is true, when 2 out of 3 inputs are true. Output is
false for all other input combinations.

Step 2) Develop a truth table for the function

Input
X Y Z
Standard Product
Terms (min-terms)
Min-term
Designators
Output
F
0 0 0
Z Y X . .
m
0
F(0,0,0) = F
0
= 0
0 0 1
Z Y X . .
m
1
F(0,0,1) = F
1
= 0
0 1 0
Z Y X . .
m
2
F(0,1,0) = F
2
= 0
0 1 1
X .Y.Z
m
3
F(0,1,1) = F
3
= 1
1 0 0
X. Y Z .
m
4
F(1,0,0) = F
4
= 0
1 0 1
X. Y .Z
m
5
F(1,0,1) = F
5
= 1
1 1 0
X.Y Z .
m
6
F(1,1,0) = F
6
= 1
1 1 1 XYZ m
7
F(1,1,1) = F
7
= 0

Note:
1) The min-term subscript corresponds to the binary value of the input.
2) All three independent input variables are present in each min-term.
3) When input is 1, the corresponding variable appears in the Min-term, otherwise the
variable is complemented in the min-term.

Step 3) Write the algebraic function equivalent to the truth table by rule:

If the output function (F) is 1 for the min-term, then the value appears in the algebraic form of
the expression.

F(X, Y, Z) = F
0
.m
0
+ F
1
.m
1
+ F
2
.m
2
+ F
3
.m
3
+ F
4
.m
4
+ F
5
.m
5
+ F
6
.m
6
+ F
7
.m
7

=

=
7
0
) . (
i
i i
m F Generalized compact Min-term form of the function
= 0.m
0
+ 0.m
1
+ 0.m
2
+ 1.m
3
+ 0.m
4
+ 1.m
5
+ 1.m
6
+ 0.m
7

F(X, Y, Z) = m
3
+ m
5
+ m
6
Compact min-term form of the function


F(X, Y, Z) =

) 6 , 5 , 3 ( m

Explicit Compact Min-term form for 1s of the function
F(X, Y, Z) =

) 6 , 5 , 3 (

Implicit Compact Min-term form for 1s of the function

By the way, the Not (Complement) of F can be written as (write the missing min-terms):
F (X, Y, Z) =

) 7 , 4 , 2 , 1 , 0 ( m

Explicit Compact Min-term form for 0s of the original function
F (X, Y, Z) =

) 7 , 4 , 2 , 1 , 0 (

Implicit Compact Min-term form for 0s of the original function

Obtaining the Standard Products of Sum (POS) Form of Functions
Although POS is not used as much, there are times where the POS form is more efficient than SOP.
As the name applies, all three independent variables are present in either complemented or un-
complemented form.
Digital Logic Design Page 43
- For each pattern, if the independent variable value is 0, it is un-complemented, and if 1, it is
complemented in the max-term which is the OR of all independent variables.
For example: X=1, Y=1, Z=0 M
6
= Z Y X + +

- Each max-term will result in the output for that term being zero.

Here is an example for a 3-input system:

Step 1) Understand the problem
Write the expression for a function that is true when more than 1 input is true, otherwise the
function is 0.

Step 2) Develop a truth table for the function and write max-terms:
All independent variables must be present in each Max-term
* It is complemented if the variable value is 1.
* It is un-complemented if the variable value is 0.


Input
X Y Z
Standard Sum
Terms (Max-terms)
Max-term
Designators
Output
F
0 0 0 X+Y+Z M
0
F(0,0,0) = F
0
= 0
0 0 1
Z Y X + +
M
1
F(0,0,1) = F
1
= 0
0 1 0
Z Y X + +
M
2
F(0,1,0) = F
2
= 0
0 1 1
Z Y X + +
M
3
F(0,1,1) = F
3
= 1
1 0 0
Z Y X + +
M
4
F(1,0,0) = F
4
= 0
1 0 1
Z Y X + +
M
5
F(1,0,1) = F
5
= 1
1 1 0
Z Y X + +
M
6
F(1,1,0) = F
6
= 1
1 1 1
Z Y X + +
M
7
F(1,1,1) = F
7
= 1


Step 3) Write the algebraic function equivalent to the truth table by rule:

For Compact Max-term Form:
If the Output function (F) is 0 for the max-term, then the value appears in the algebraic form
of the expression.

F(X,Y,Z) = (F
0
+ M
0
). (F
1
+ M
1
). (F
2
+ M
2
). (F
3
+ M
3
). (F
4
+ M
4
). (F
5
+ M
5
). (F
6
+ M
6
). (F
7
+ M
7
)
= ) (
7
0
i i
i
M F + H
=
Generalized compact max-term form of the function

Note the when F
i
=1, the max-term is not needed --- for our example:
F(X,Y,Z) = (0

+ M
0
). (0

+ M
1
). (0

+ M
2
). (1

+ M
3
). (0

+ M
4
). (1

+ M
5
). (1

+ M
6
). (1

+ M
7
)
F(X,Y,Z) = M
0
. M
1
. M
2
. M
4
Compact Max-term form of the function

Other forms:
F(X,Y,Z) = ) 4 , 2 , 1 , 0 ( M H

Explicit Compact max-term form for 1s of the function
F(X,Y,Z) = ) 4 , 2 , 1 , 0 ( H

Implicit Compact max-term form for 1s of the function

The Not (Complement) of F can be written by writing the missing max-terms for Un-
complemented F:
Digital Logic Design Page 44
F (X,Y,Z) = ) 7 , 6 , 5 , 3 ( M H

Explicit Compact max-term form for 0s of the function
F (X,Y,Z) = ) 7 , 6 , 5 , 3 ( H

Implicit Compact max-term form for 0s of the function

Relationship between Min-terms and Max-terms
Min-terms and Max-terms are complements of each other :
i i i i
m M and m M = =
DeMorgans Theorem is key to proving the min-term/max-term relationship:

a)
n n
X X X X X X - - - = + + +
2 1 2 1

b)
n n
X X X X X X + + + = - - - . .
2 1 2 1


Examples:
Given max-term M
6
= Z Y X + + . , find min-term m
6
.

1) Since it is a max-term, when X=1, Y=1 and Z=0 Then F(X,Y,Z) = 0
2) To convert to Min-term we can apply DeMorgans Theorem which in practice is dividing up
the overbar. This means that the cross bar can be divided across its subpart while accepting the
rules:

+ = = + . . and

Lets see how it applies to our example.

We know that
i i i i
m M and m M = = so

Z Y X Z Y X Z Y X m term Min
i
. . . = + + = + + = =

Example: Apply the overbar to finding Complement of F if F(X,Y,Z) = ) ).( . ( Z Y Y X + +

Solution:
Apply the DeMorgans Theorem in the form of Dividing up the Overbar.
Z Y Y X Z Y Y X Z Y Y X Z Y Y X Z Y X F . . ) . ( ) . ( ) ( . ) ( ) ).( ( ) , , ( + = + = + + = + + =


Example
Write Standard SOP and POS form for f(x
3
, x
2
, x
1
, x
0
) =

) 15 , 12 , 7 , 0 (
Solution:









Converting between compact forms of functions
Digital Logic Design Page 45
We can extend the relationship between max-terms and min-terms to include SOP (Sum of
Products) and Products of Sum (POS):

[ [
= =
= =
and
m M and m M
i i i i


Example:
Write the F(A,B,C)=
[
) 6 , 5 , 3 , 0 ( in the compact min-term form.

We know that
[
= Therefore

) ).( ).( ).( ( ) 6 , 5 , 3 , 0 ( ) 6 , 5 , 3 , 0 ( ) , , ( C B A C B A C B A C B A C B A F + + + + + + + + = = =
[

Since these terms are the 0s of the function, if we write the Min-terms that are not present then
we will have the 1s of the function:
C B A C B A C B A C B A C B A F . . . . . . . . ) 7 , 4 , 2 , 1 ( ) , , ( + + + = =

Example
Use only NAND gates to implement f(a
2
, a
1
, a
0
) = a
2
.a
1
.a
0
+ a
2
.a
1

.a
0

+a
2

.a
1

.a
0


Solution:






Example
Use only NOR gates to implement f(a
2
, a
1
, a
0
) = (a
2

+a
1
+a
0

) + (a
2

+a
1

+a
0
) + (a
2

+a
1
+a
0
)

Solution:







Digital Logic Design Page 46
2.8. Methods of Function Minimization (reducing the number of literals in an expression)

It is important to minimize the function prior to implementation. Minimization of literals and operators
reduces the number of gates needed to implement the function therefore reducing the cost of
implementation. In this section Systematic Algebraic Reduction (SAR) minimization techniques will be
discussed. The SAR technique is effective for automation but tedious for human use. On the other hand,
Karnaugh Map (K-Map) that will be discussed later is a visual tool that is more effect for human use to
minimize functions.
.
.
Systematic Algebraic Reduction (SAR) technique uses algebraic theorems and postulates. Although
you could start applying various algorithms until you find one that reduces the function, our goal is to
introduce systematic techniques that can be described in a step-by-step process (algorithm) and
consistently applied.

Usage
Most Computer Aided Design (CAD) packages use the SAR technique for function minimization.
Although SAR is not guaranteed to reduce the function to a minimum, it is the most effective
algorithm available.

Process
Here is the step-by-step algorithm for a Systematic Algebraic Reduction(SAR):
(1) Expand the function into its Standard sum of products (SOP) form
(Include all variables; writing variables in order in all terms makes it easier to recognize
patterns.)

(2) Compare all pairs of products for:
(a) Adjacency Theorem: 1 exp 2 exp . 1 exp 2 exp . 1 exp = +
and
(b) Idempotency Theorem: exp exp exp = +

**Note: The reduction process may have to be repeated a number of times.

(3) Once you have done all reductions possible in step 2, See if the Consensus Theorem
applies
3 exp . 1 exp 2 exp . 1 exp 3 exp . 2 exp 3 exp . 1 exp 2 exp . 1 exp + = + +

Example: Using SAR, minimize the function F= ) ).( ).( ( C B C A C B A + + + +
Solution:
1) Use the truth table to derive the min-terms

A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

2) Write the function in compact Min-term form
Digital Logic Design Page 47
F = C B A C B A C B A C B A . . . . . . . . + + +

3) Apply Adjacency Theorem to all pairs as possible.
(another way is drawing double head arrows showing relationship between two terms)


C A C B A C B A Term
C B C B A C B A Term
Appicable Not Term
Applicable Not Term
C B C B A C B A Term
C A C B A C B A Term
. . . . . ) 4 & 3 (
. . . . . ) 4 & 2 (
) 3 & 2 (
) 4 & 1 (
. . . . . ) 3 & 1 (
. . . . . ) 2 & 1 (
= +
= +


= +
= +


Therefore:
F= C A C B C B C A . . . . + + +

4) Perform a second pass of Adjacency theorem.

F= C A C B C B C A . . . . + + +

Therefore:
F= C + C = C

In this case we did not need to apply the Consensus Theorem since the answer cannot be
simplified further.

In general, Systematic Algebraic Reduction (SAR) methods are best suited for computer
programming. K-maps, which will be described in the next section are best suited for human use
up to 4 variables since it is graphic.

c
C
Digital Logic Design Page 48
2.9. Karnaugh-map or K-map
K-map is the best tool for minimization of five or fewer variables functions for humans. K-maps are
graphic and require pattern-matching which is one of humans strongest abilities. Many believe that
humans solve problems by creative pattern-matching.

K-map is a number of squares which are labeled using reflective gray code (each code is only 1
change from an adjacent code). For a given square, the user enters 0 or 1 corresponding to the
function value at the inputs represented by the labels.

Here are K-map examples for 2, 3, and 4 Variables:

Each of the squares will contain a 1 if the function is 1 (min-term locations) and 0 otherwise. You
may also use -, which reflects the dont care (can be 0 or 1, whichever gives us the lowest
Literal Count, LC).

The Literal Count (LC) is proportional to the number of gates needed during the implementation,
so the less the better.

Here is the location of each min-term on a Karnaugh-Map:


0 1
2 3
0 1
0
1

F(A,B)=AB
2-Variables
B
A
0 1
2 3
0 1
00
01
11
10

F(A,B,C)
3-Variables
C
AB
6 7
4 5
0 1
4 5
00 01 11 10
00
01
11
10
F(A,B,C,D)
4-Variables
CD
AB
3 2
7 6


12 13 15 14
8 9 11 10
A B C D Min-term,m
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15

F(A,B)
2-Variables

F(A,B,C)
3-Variables
F(A,B,C,D)
4-Variables
0 0
0 1
0 1
0
1
B
A
1 0
0 0
0 1
C
AB
0 1
0 0
1 1
0 0
00 01 11 10
00
01
11
10
CD
AB
0 1
1 0
1 1
1 0
0 1
0 1
00
01
11
10
Digital Logic Design Page 49
Example: Use K-map to minimize F(A,B,C) = C B A C B A C B A C B A . . . . . . . . + + +
Solution:
1. Use a truth table to identify all the Min-terms (Over time you can do this mentally, so it would
not be necessary to draw it).

A B C F Min-term, m
i

0 0 0 0 0
0 0 1 1 1
0 1 0 0 2
0 1 1 1 3
1 0 0 0 4
1 0 1 1 5
1 1 0 0 6
1 1 1 1 7

2. Fill in the K-map:
a. Select the K-Map that matches the number of variables in your function, (3 for the
Example)
b. Draw the K-map (remember the labels are reflective Gray Code)
c. Enter the value of the function for the corresponding min-term. If the value of the
function is unspecified then enter which means dont care.


3. The next step is to group as many neighboring ones as possible. Cells with one variable is
complemented are referred to as neighboring cells:
a. Grouping adjacent min-terms (boxes) is applying the Adjacency theorem graphically,
i.e.
C C A C A = + . . .
b. The goal is to get as large a grouping of 1s as possible
(Must form a full rectangle cannot group diagonally)
0 1
0 1
0 1
00
01
11
10

F(A,B,C)
3-Variables
C
AB
0 1
0 1
Digital Logic Design Page 50



4. For each identified group, look to see which variable has a unique value. In this case,
F(A,B,C) = C since Fs value is not dependent on the value of A and B.

More K-map related definitions:
Example: A function with the following K-Map

An Implicant is the product term where the function is evaluated to 1 or complemented to 0. An
Implicant implies the term of the function is 1 or complemented to 0. Each square with a 1 for the
function is called an implicant (p). If the complement of the function is being discussed, then 0s
are called implicants (r).
Note: To find the complement of F, apply the same rules to 0 entries in the K-map instead of 1.

A Prime Implicant of a function is a rectangular (each side is powers of 2) group of product
terms that is not completely contained in a single larger implicant.

An Essential Prime Implicant of a function is a product term that provides the only coverage for
a given min-term and must be used in the set of product terms to express a given function in
minimum form.

An Optional Prime Implicant of a function is a product term that provides an alternate covering
for a given Min-term and may be used in the set of product terms to express a function in a
minimum form. Some functions can be represented in a minimum form in more than one way
because of optional prime implicants.

A Redundant Prime Implicant or Nonessential Prime Implicant of a function is a product term
that represents a square that is completely covered by other essential or optional prime
1 1
0 1
00 01 11 10
00
01
11
10
F(A,B,C,D)
4-Variables
CD
AB
0 0
1 0
0 1
1 0
0
0 0
1
Redundant Implicants
Essential Prime
Implicant
(Optional) Prime
Implicant
Minimized function = C B A D B D C B . . . . . + +
0 1
0 1
0 1
00
01
11
10

F(A,B,C)
3-Variables
C
AB
0 1
0 1
Digital Logic Design Page 51
Implicants.

Example: Write the minimized SOP function represented by the following K-Map

Solution:









Example:
use K-map to write the minimized SOP and POS forms of the following function:

= ) 27 , 26 , 25 , 24 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 ( ) , , , , ( E D C B A F

Solution:








Example:
use K-map to write the minimized SOP and POS forms of the following function:

[
= ) 15 , 13 , 10 , 8 , 2 , 0 ( ) , , , , ( E D C B A F

Solution:











1 1
1 1
00 01 11 10
00
01
11
10
CD
AB
0 1
0 0
0 0
1 0
1 1
1 1
Digital Logic Design Page 52
2.10. Special Case: Dont Care Terms
In K-map, we can use the unspecified values of a function dont care as 1 or 0, allowing us to create
larger cubes to write products with smaller Literal Count (LCs)
Example: F(W,X,Y,Z) with unspecified values (dont cares, -)


We have an option of assuming - as 0 or 1 whichever ends up with a lower Literal Count (LC)
and therefore lower hardware (gates) cost during the implementation phase. Here is one
minimized function representing the K-Map function:


F(W,X,Y,Z) = Y X W Z Y Z W Z Y X . . . . . . + + +
For this function the Literal Count (LC) is 10.

Sometimes it makes sense to use the 0s and write the complement to get a lower LC.

) , , , ( Z Y X W F = Y W Z X Z Y W . . . . + +
For this function, the Literal Count (LC) is 7.

Function in POS form
) , , , ( Z Y X W F = ) ' ).( ).( ' ' ( Y W Z X Z Y W + + + +

Representing dont care min-terms in compact form.
-

) 5 , 4 , 1 ( md md refers to dont care min-terms.

0 1
1 1
00 01 11 10
00
01
11
10
YZ
WX
- -
- 0
1 0
0 -
1 1
1 0
0 1
1 1
00 01 11 10
00
01
11
10
YZ
WX
- -
- 0
1 0
0 -
1 1
1 0
0 1
1 1
00 01 11 10
00
01
11
10
YZ
WX
- -
- 0
1 0
0 -
1 1
1 0
Digital Logic Design Page 53
2.11. XOR Properties and Applications
K-map patterns
Checkerboard pattern: alternating cells and diagonal cells of 1s and 0s on a K-map is a sign of XOR
or XNOR.

XOR properties:
Commutative
A B C C B A =

Associative
A B C C B A = ) ( ) (

Rubber band effect (The bar can be put anywhere and the result remains unchanged)
B A B A B A B A = = =

XOR is 1 when there is an odd number of 1s in the XOR operands
Note: This feature is used to do single bit error checking, which is adding an extra bit to the
data to ensure that the number of 1s is odd. (This is known as odd parity).

XNOR is 1 when there is an even number of 1s in the XNOR operands
Note that this feature is used to do single bit error checking, which is adding an extra bit to
the data to ensure that the number of 1s is even. (This is known as even parity).

XNOR 4-bit Comparator Design



A
0

B
0

1 if A
0
= B
0

A
1

B
1

A
2

B
2

A
3

B
3

A=B 1 if A
0
= B
0
and
A
1
= B
1
and A
2
= B
2

and A
3
= B
3
.
0 1
0 1
1 0
1 0
AB
C
0 1
00
01
11
10
0 1
0 0
1 0
0 0
AB
C
0 1
00
01
11
10
0 0
0 0
1 1
1 1
AB
C
0 1
00
01
11
10
Checkerboard pattern
F = C B A
Diagonal Cells
F = ) .( C B A
Alternating Cells
F = B A
Digital Logic Design Page 54
2.12. Additional Resources

Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 4 Combinational Logic Design Principles
Digital Logic Design Page 55
2.13. Problems
Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.


Digital Logic Design Page 56
Chapter 3. Analyzing and Synthesizing Combinational Logic Circuits

3.1. Key concepts and Overview

Standard Logic and Schematic Layout
Designing Logic Circuits
Compressing Truth Tables & K-Maps
Glitches and Hazards
Types of Functions and Delays
Beyond Standard Logic (Encoders, Decoders, PLD, GAL, ROM, PROM, )
Additional Resources
Problems

Digital Logic Design Page 57
3.2. Standard Logic and Schematic Layout (Review)
This section describes Small Scale Integration circuits which are commonly used for smaller projects. It
also provides an understanding of the basics of computer design.

Basically, computers regardless of complexity, can be designed using these simple gates as building
blocks. We will start by discussing the most fundamental gates which are AND, OR and NOT.


AND Function (F=A.B)

Truth Table
A B F
0 0 0
0 1 0
1 0 0
1 1 1

Symbols & Operation
- Recommendation is to use the shapes for simple gates; and box (non-shape) for more
complex logic
- When using in a schematic mark the IC ID (D#) and Pin # on the schematics
- A couple of other representations using switches (Relays, Transistors)



U
A
B
F
A

B
F
&

U
F
A B
n.o. n.o.
Vcc = H = 1
n.o.
n.o.
n.c. n.c.
GND = L = 0
F 0=L=V
L

1=H=V
H

IEEE: Shape Distinctive Graphics
IEC: Non-Shape Distinctive
Graphics Symbol
Pass Logic Switching Circuit
0: Button is Not pressed
1: Button is pressed
Regenerative Logic Switching
Circuit
A
B
1
2
3
1
2
3
Digital Logic Design Page 58
Different Switches
Instead of mechanical switches, we can also use electronic switches:

A normally open (n.o.) switch is closed when pressed.

A normally close (n.c.) switch is open when pressed


Example of setting up a LED and a switch


U
A
B
F
1
2
3
GND
GND
R
R
F=1 LED on
F=0 LED off
Vcc
Switch open F=1
Switch closed F=0
Note: Typically R=1 kO is used.
N

-
V
+
When Current Flows the
Relay opens
Spring
contact
Relay as n.c.
Gate
Source
Drain
Base
Emitter
Collector
PMOS FET as n.c.
Ngative Channel Mtal
Oxide Semiconductor

Field Effect Transistor
PNP BJT as n.c.
Bipolar Junction
Transistors
N


-
V
+
When Current Flows the Relay
closes
Spring
contact
Relay as n.o.
NMOS FET as n.o.
Positive Channel Metal Oxide
Semiconductor

Field Effect Transistor
NPN BJT as n.o.

Bipolar Junction Transistors
Gate
Drain
Source
Base
Collector
Emitter
Digital Logic Design Page 59
Physical packaging



Through Hole Device ( 2 to 100 pins)




Surface Mount Device Package (2 to 100 pins)




PIN Grid Array (>100 pins)



Digital Logic Design Page 60
Number of possible functions for an n-variable input equals
) 2 (
2
n

For example, a device with 2 input may have one of the possible
) 2 (
2
2 =2
4
=16 functions.

2-Input
X Y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
GND And OR Vcc

Analyzing Logic Circuits
- Draw a system diagram and identify input/output signals

- Based on the schematic, write out the Boolean algebraic equation
f(x, y, z) = ?

- Based on the equation, do the K-map or truth table

- Review the truth table to understand the function of the circuit

Example
Analyze the following circuit:

- System Diagram

System
A


B
F(A,B)
B
F(A,B)
A
System
X1
.

X
n

Y1
.

Y
n

Digital Logic Design Page 61
- Algebraic equation
F(A,B) = {(A.B).(A.B)}

- Truth Table
A B F(A,B)
0 0 0
0 1 1
1 0 1
1 1 0

- This circuit is implementing an exclusive OR.

Digital Logic Design Page 62
3.3. Designing Logic Circuits
The process of combinational logic design is best described in six steps:

1) Draw the system diagram and identify input and output variables.
2) Write out the truth table for the function.
3) Use K-maps or CAD to minimize the function and write the algebraic function.
4) Identify the logic gates required and draw the schematic to implement the terms of the
algebraic function. The schematic should include:
- Designer and project name.
- Component identification and pin numbers.
- List of all the pins that are connected to Vcc and Ground, and are not use.
All Connecting lines must be either vertical or horizontal (No diagonal or curved lines).
Additionally, a dot is used to mark an actual connection when two lines cross over each
other.

Note: Hardware Description languages such as VHDL or Verilog HDL or State CAD by Visual
Software Solutions, can also be used to document the design.

5) Implement (pay attention to layout and ease of support/use).
6) Test (each design must have a test plan).

Remember that the design process is an iterative process; it is important to use the learning from
later steps of the design process to improve earlier work. The best designs typically have many
design iterations before the final design has been completed.

Example
Design a 4-key digital lock that can be opened only when every other keys are pressed.

Project Name
Designer Name
Date
ID Component Desc. No Conn. Vcc Gnd
U1 U1, 74LS32 4-6, 8-13 14 7
X
Y
Z U1
3
1
2
Vcc
Gnd
1kO
1kO
Digital Logic Design Page 63


Solution:

1) Draw the system diagram and Identify input and output variables..


- Input and output value definition:
K
i
=1 when key i is pressed and K
i
=0 when key i is not pressed.
L
0
=1 causes the lock to open

2) Write out the truth table for the function:

Input Output
K
0
K
1
K
2
K
3
L
0

0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

3) Use K-map or CAD to minimize the function and write the algebraic function.







Key
Controller
K
0


K
1


K
2


K
3

L
0

K
0
K
1
K
2
K
3
Keypad
Digital Logic Design Page 64







4) Identify the logic gates required and draw the schematic to implement the terms of the
algebraic function.


5) Implement (pay attention to layout and ease of support/use).

6) Test (outline test plan).


Example
Design a 4-key digital lock that can be opened only when 2 or more adjacent keys are pressed.



Solution: Student Exercise.

K
0
K
1
K
2
K
3
Keypad
Project:
Designer:
Date:
ID Component Desc. No Conn. Vcc Gnd




Digital Logic Design Page 65
Fan-out and Fan-in
1) Fan-out: The number of gate inputs that can be driven by a single output (for LS chips. the
fan-out limit is 20)
2) Fan-in: The number of gate inputs that may be connected together. Typically, fan-out is the
limitation factor for LS.


Using NAND or NOR gates
NAND and NOR gates can be substituted for each other. Basically, NOR implements POS and
NAND implements SOP. A function can equally be written as POS or SOP.

We will explore NAND gates here and similar concepts also apply to NOR gates.

NAND is one the most desirable basic gates for three reasons:

1) NAND gates are faster than other gates such as AND.
2) NAND gates can be used to make all other gates such as inverters, ANDs and ORs
(Demorgans Theorem is the basis of this statement.)

Therefore NAND is said to be functionally complete since it can be used to build any other
function. Below are examples of Inverter and OR function implementation.

3) NANDs are available in more variety (#of input) than AND, OR gates


INVERTER OR
Digital Logic Design Page 66
3.4. Combinational Logic Analysis and Design
Below is a summary of design and analysis process steps for a combinational logic device:


Device
Schematics
Functional
Definition
Design Process
1) System Diagram
2) Truth Table
3) K-Map
4) Ouput Expression
5) Schematics
Analysis Process
1) System Diagram
2) Output Expression
3) Truth Table
4) Functional Definition
Digital Logic Design Page 67
3.5. Compressing Truth Tables and K-maps

The process of compressing truth tables.
Truth table compression is done by:
1) Row compression(use OR function).

A B F2 F2
c

0 0 0 F2(0,B)=0
0 1 0
1 0 1 F2(1,B)=
B
1 1 0

In the above table, we are applying Shannons Expansion Theorem
B B B B F B B F B F = + = = + = = 0 . 1 . ) 1 ( .. ) 0 ( . ' 2 which can be compressed to

A F2
c

0 0
1
B


2) In general, any truth table can be compressed by applying the Shannons Expansion
Theorem with respect to the least significant bit, as shown below:

A B C F3 F3
c

0 0 0 0 0
0 0 1 0
0 1 0 0
C
0 1 1 1
1 0 0 1 1
1 0 1 1
1 1 0 1
C
1 1 1 0

So we can compress it to

A B F3
c

0 0 0
0 1 C
1 0 1
1 1
C

Example
Compress function F(x,y,z) = (1,3,6,7):
a) about z
b) about x
a) about x, y & z

Digital Logic Design Page 68
The concept of compressing around a variable using Shannons Expansion Theorem also applies
to K-maps. The example below uses C as the reference variable:

4-variable (multivariable) expression of K-map Compression.



Plotting, Filling, and Reducing Compressed K-maps
The steps to compress a K-map are:
(1) Plot the truth table and then compressed K-map.
(2) Choose cube sizes that result in minimum expressions for the function by covering each
map-entered variable separately, treating other map-entered variables as 0s and all 1s as
dont cares.
(3) Choose cube sizes that result in minimum expressions for the function by covering the 1s
in the map that are not complementary-covered.
WX F
0 0
Y
0 1
Z Y Z Y . . +
1 1
Z Y Z Y . . +
1 0
Z Y.
W X Y Z F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
1 1
1 0
00 01 11 10
00
01
11
10
YZ
WX
0 0
1 0
1 0
1 0
1 0
0 0
1 0
Z
Z
0 1
Y
WX
Z
0
00
01
11
10
Compare
Compare
Z
Z
Compare
0 0
0 1
0 1
C
AB
1 0
1 1
00
01
11
10
O
C
AB
C
1
00
01
11
10
K-map
Compressed K-map
Compare
Digital Logic Design Page 69
Example of plotting, filling and reducing a compressed K-map directly from the compressed K-
map and expanding to an uncompressed form.


A 6-variable example of compressed K-map is described by:

+ = ) 13 ( ) . 15 , 14 , . 12 , 7 , . 6 , 5 , 4 , . 1 , . 0 ( ) , , , , , ( md Z Y Z Y Y Z Y D C B A F
Where m = m(A,B,C,D)

Minimize the function.

AB CD
00 01 11 10
00
01
11
10
Y
0 0
Y
1 1 Z 1
Y Z 1 -
0 0 0 0
AB CD
00 01 11 10
00
01
11
10
Step1. Compressed K-Map
Step 3.
Map-entered variable 0
Complementary-covered 1 dont care
1 1 & 0 0

Step 2.
1 dont care
0 0
No change to Variables


Implicants: Group variables
Individually
AB CD
00 01 11 10
00
01
11
10
Y
0 0
Y
- - Z -
Y Z - -
0 0 0 0
p2
p3
p1
0 0 0 0
- 1 0 -
0 0 1 -
0 0 0 0
P4
p5
0
Z
1
Z
XY
00

01

11

10
0
0
1
1
XY Z
00

01

11

10
0
1
1
0
0 1
Compressed K-Map Uncompressed K-
Map
Definition: A complementary covered 1 in a compressed K-map is a 1 that is covered
with a map-entered variable and covered again with the complement same map-
entered variable.
p3 = X.Y
(Redundant Prime Implicant)
p1 = Y.Z
p2 = Z X.
F(X,Y,Z)= Y.Z+X. Z
Digital Logic Design Page 70
F(A,B,C,D,Y,Z) = p1 + p2 + p3 + p4 + p5 = D B A D C B A Y C B Y C A Z C B . . . . . . . . . . . + + + +

Although you can use the compressed K-map and apply both steps, it is recommend that you
draw both graphs until you are comfortable with the process.

Digital Logic Design Page 71
3.6. Glitches and Their Causes

A glitch is a momentary error condition on the output caused by unequal signal paths delays in the
circuit. This may appear as an additional pulse high or low that will go away once the circuit reaches
a steady state condition (after the signal has propagated through the circuit completely)

Glitches can occur when a hazard condition exists (Function and Logic Hazards)

1) Functional Hazard
Exists when there is a problem due to two or more inputs are changing at the same time.
May be static when output is not changing or dynamic when the output changes.
Cannot be removed by additional circuitry

2) Logic Hazards
(1) Exists when there is a problem due to a single input change.
(2) May be static when output is not changing or dynamic when the output changes.
(3) Can be removed by additional circuitry

Example: Use Function F(A,B,C)= C B C A . . + to show both function and logic static hazards
Static means before and after the Glitch the output is the same
(User DeMorgans Theorem to use only NAND Gates)

Step 1. Generate a K-map and draw a schematic. Both of these drawings will assist in
identifying unequal propagation path and, therefore, delays through the circuit.



Step 2. Take a look at any logic static hazards that exist and if they may cause a glitch.
Note: when a single input is changing.

00
01
11
10
0 1
AB
C A
C
B
F
0
0
0
1

0
2
1
3

1
6
1
7

1
4
0
5

C1
Digital Logic Design Page 72

Step 3. Take a look at any Function Static hazards that exist, and if they may cause a Glitch.
Hint: Look for two or more input changing simultaneously.

**Note: A system hazard does not have any impact on the functionality if:
- The inputs are not changed to trigger the hazard condition.
or
- The output will not be used until the input is stabilized.

00
01
11
10
0 1 A
C
M4(100) m3 (011)
Function static Hazard
A
B
C
C1
F
During NAND Propagation delay C=C1=0 therefore F=0 during the delay which is a Logic 0 Glitch.
F= 1 1
so is a static 1 hazard logic 0 glitch
1
6

0
0
0
1

0
2
1
3

1
7

1
4
0
5

Side Bar
If F=0 0 but has a high glitch, then it is
called static 0 hazard. For example, m
0

to m
5
.
F
Logic 1 glitch

F= 0 0 so static 0
hazard
00
01
11
10
0 1
A
C
1
6

0
0
0
1

0
2
1
3

1
7

1
4
0
5

m
7
(111) m
6
(110)
Logic static Hazard
A
B
C
C1
F
During NAND propagation delay C=C1=0; therefore
F=0 during the delay. This is a Logic 0 Glitch.
To remove this logic static
hazard, add a term that covers
both m6 & m7
00
01
11
10
0 1
AB
1
0 0
0 1
1
1 0
F(A,B,C)= B A C B C A . . . + +
This is a logic hazard-free
function
The process is called the Chain
Link Rule.
C
Digital Logic Design Page 73
Dynamic Hazards
A dynamic hazard occurs when an output changes from 0 to 1 or from 1 to 0.
(in static hazard case: output before and after the glitch was the same)

- Typically dynamic hazards are produced by multi-level or cascading logic circuits

- Example F= C B A which means F=1 when odd number of inputs are 1. Identify
dynamic hazards in this circuit.

Step 1. Do the K-map

Depending on the amount delay through each gate, you may or may not have a dynamic
hazard. Typically, simulation software such as B2 Logic , PSpice, and Electronic Work
Bench is used to compare maximum and minimum propagation delay for each component to
find any dynamic hazards.

If we assume the right amount of delay through the gate, it can be shown that we can cause
dynamic hazards in the following paths:

Dynamic hazards are by far the hardest problem to identify. Once the hazards are identified, strategic
delays can be implemented to correct the problems.

Logic 1 glitch
Cell 5 to 2 or Cell 6 to 1
causes Dynamic 1 to 0 hazard
F2 (10)
t
Logic 0 glitch
Cell 2 to 5 or Cell 1 to 6
causes Dynamic 0 to 1 hazard
t
F2 (01)
0
0
1
1
1
2
0
3
0
6
1
7
1
4
0
5
00
01
11
10
0 1
AB
C
Logic 1 glitch
Dynamic 1 to 0 hazard
F2
t
Logic 0 glitch
Dynamic 0 to 1 hazard
t
Digital Logic Design Page 74
3.7. Types of Functions and Delays

Trivial Functions, one or zero input
- GND, Vcc, Buffer, and Inverter
We use t
p
to refer to propagation delay through a gate.

Simple Functions contain one sum or one product but may be complemented
- For example:


- Simple functions may be one or two-level depending on the complements.
- To find the delay through a gate you need to refer to the parts specification from the
manufacturer.
- For example a 74LS02 (NR gate) for R
L
= 2Kohms and C
L
= 15 pF:
(a) Maximum propagation delay time Low to High Level output t
PLH
= 13 ns
(b) Maximum propagation delay time High to Low Level output t
PHL
= 10 ns
(c) Sometime we use the average worst case propagation delay time
t
su
=( t
PLH
+ t
PHL
)/2
(d) To find the maximum delay through a cascading circuit, t
p
of each component in the
path must be added to find the total worst case delay through the circuit.

Complex Functions contain multiple levels of sums and/or products
- The delay for each path needs to be calculated by adding the propagation delay, t
p
, for each
component in the path. For example
If the t
p
is the time delay for each component then:
* delay from input A to output F is 3*t
p
.
* delay from input C to output F is 4*t
p
.

- For a multi-output complex function, at times there is an opportunity to share product terms
among the outputs to lower Literal Count (LC) and, therefore, reducing the number of gates.


A
F
C
Digital Logic Design Page 75
- Example: Given the following K-maps for F1 and F2 outputs of a three input system, find the
optimum design:

- Commonly-used complex functions have been implemented as ICs, and are crucial to the
ability to develop complex functionality. Using individual gates consumes too much PC board
space and wiring to be realistic.

The next section introduces some of the most common complex function available on the
market.

00
01
11
10
0 1
AB
C
F
1
(A,B,C) = C C B A + . .
1
0
1
1

1
2
0
3

1
6
0
7

1
4
0
5

C
F
2
(A,B,C) = C B C B A . . . +
0
0
1
1

1
2
0
3

1
6
0
7

0
4
0
5

AB
A smaller F
1
could have been written, but the fact that m
1
can be shared between F
1

and F
2
, results in a more minimized total solution (F
1
and F
2
).
0 1
00
01
11
10
Digital Logic Design Page 76
3.8. Beyond Standard Logic: Applications
Precision Timers 555
This device is a precision timer that may be configured for a variety of applications. The most
common use of the NE 555 is an application to generate square waves that may be used as a clock
signal in digital design. In order for NE 555 to generate the clock signal, it may be configured as
shown below:



Example
Given the component values in the introduction of NE 555 (above), draw the clock (square wave)
signal generated and determine the period, frequency and duty cycle for the signal.

Solution:











Digital Logic Design Page 77
Example
Using 555 timer, design a circuit that generates a clock signal with frequency of 2.5 Khz and 75%
duty cycle. Show your work including component value calculations, timing diagram and resulting
schematics.

Solution:






Digital Logic Design Page 78
Encoders
Function: 2
n
input n output
Example: 74LS148 "8 to 3 encoder"
Note: You can design these circuits using the 6-step design, K-map, and SSI gates.





Notes:
EI is the output-enable input and should be set to L for normal operation.
Remember that:
L is the same as 0, Gnd or 0 volts.
H is the same as 1, Vcc or +5 volts.
X means dont care, it can be high or low.

Digital Logic Design Page 79


Digital Logic Design Page 80
Decoder, also called minterm generator
Function: n input 2
n
output
Example: 74LS138 "3 to 8 Decoder/Demux"





Digital Logic Design Page 81


Digital Logic Design Page 82
BCD to 7-segment display driver
Function: Binary Coded Decimal Digits (4 inputs 0-9) 7 output one per segment
Example:74LS47


74LS47
Digital Logic Design Page 83


Note: The output is active low and open collector:
- H, Inactive and OFF are same
- Active, L and ON are the same.
- In order to light up LEDs, each LED in the 7-segment display should be wired as shown below.

The 1 K resistors limits the current through the LED to 5 mA.
Output
1 K
Vcc
Cathode LED Anode
74LS47
Digital Logic Design Page 84


74LS47
Digital Logic Design Page 85
3.9. Programmable Logic Devices (PLDs)
PLDs allow a designer to implement his/her design on a single chip. The main advantages of PLDs are
speed of implementation, ease of implementation and low overall cost at low quantities. Most projects
use PLDs during the design phase because of the stated reasons. During production when the quantities
are higher, the design is typically implemented with one-time factory-programmed devices that are able to
implement the design.

A summary of PLDs is shown below the size in-terms of input/output and function, is growing on a daily
basis. Most designs will prototype using one of these devices until they have enough quantity to justify a
custom chip.

Device Type AND Array Connection OR Array Connections
PROM -Programmable Read Only
Memory
Fixed at the Factory Customer programmable
with Fuses

PLA - Programmable Logic Array Customer programmable
with Fuses
Customer programmable
with Fuses

PAL Programmable Array Logic,
also called GAL - Generic Array Logic

Customer programmable
with Fuses
Fixed at the Factory

Introducing Key Symbols used in PLD Design
- Fuse Types Symbols

(1) Product Terms (Example)
(a) The output has a pull-up resistor that is not shown, and if all fuses are blown then the
output will be H.
(b) If all fuses are intact, then they may place an X in the And symbol.


(2) Sum Terms (Example)
(a) The output has a pull-down resistor (not shown), and if all fuses are blown, then the
output will be L.
(b) If all fuses are intact, then they may place an X in the OR Symbol.
A
1
A
0

0 1
.A A
No Fuse
Fixed Connection at
factory
Intact Fuse
Programmable
Connection
Blown Fuse
Connection Broken after
Programming
Digital Logic Design Page 86

(3) Erase ability
Some devices allow the blown fuses to be re-fused by:
(a) Ultraviolet Light (through a small window on the top)
(b) Electrically (typically at much higher voltage and current than normal operation)
This type is referred to as EE-type.

There are also universal programming units available that allow for fuse map input/output which
adheres to the Joint Electronic Device Engineering Council (JEDEC) Standard.

Programmable Read Only Memory (PROM)
A typical PROM may have 16 inputs with 2
16
outputs. This device would be called a 64K PROM.
PROM is typically used during development and once the product is in production, Read Only
Memory(ROM) will be used.

ROM is a one-time factory-only programmable device which is the reason why it is called Read
Only Memory. The initial ROM set up is costly but the cost per part is significantly lower than that
of PROM.

The following diagram shows the PROM internal diagram:


PROM Example: Implement F(A
0
,A
1
)=
1 0 1 0
. . A A A A +

Since all the minterms are available, all we have to do to get the desired output is to OR the
appropriate minterms and then blow fuses for all the minterms not needed for the function.
A
n
(MSB) A
0
(LSB)
m
0

m
1

m(
2
n+1
-1)
Factory set
Intact Fuse
n-bit input
AND array connections
are set in factory F
0
F
m

Programmable OR array connections
p
3
p
2
p
1
p
0

p
0
+ p
3

Digital Logic Design Page 87
F(A
0
,A
1
)=(1,2), which means fuses 0 and 3 need to be blown.


Example
Draw the fuse map for the smallest PROM that implements the function:

f(a
2,
a
1
,a
0
) = a
2
.a
1
.a
0
+ a
2
.a
1
.a
0
+ a
2
.a
1

Note: Only draw the minterms that are used

Solution:
























A
1
A
0

m
0

m
1

F
0

m
2

m
3

Fuse Map
Digital Logic Design Page 88
Example
Use a PROM to design a 4-byte memory that contain 10, 50, 90 and 20 in location 0 to 3.
Show the system diagram and PROM fuse map.
Note: Only draw the minterms that are used

Solution:













Digital Logic Design Page 89
Programmable Logic Arrays (PLA)
PLAs are similar to PROMs with the added flexibility of programmable AND array connections.
PLAs are the most flexible of the Program Logic Devices since both the AND and OR array
connections are field programmable. The drawbacks of the PLA technology are that they have
the highest cost per unit and the longest propagation delays.

PLA Example: Implement F(A
0
,A
1
)=
1 0 1 0
. . A A A A +
PLAs allow both the AND and OR array connections to be programmed. The complete fuse
map shows both the AND and the OR fuses. There may be opportunities to share product
terms between the outputs to improve efficiency.

0
0
1
1
1
2
0
3
0
1
0 1
A
0

A
1

p2
p1
A
n
A
0

p
0

p
1

p
(2
n+1
-1)

Factory set
Intact Fuse
n-bit input
Programmable AND array
connections
F
0
F
m

Programmable OR array
Digital Logic Design Page 90



Programmable Array Logic (PAL) or Generic Array Logic (GAL)
PAL and GAL are two different way to refer to this technology. PALs are:

- Easiest to use, since only the AND array connection is programmable.
- Best suited for non-standard complex combination logic implementation.
- Available in variety of sizes. The larger versions are called Field Programmable Gate Array
(FPGA). The version that can be configured at the factory for larger volume design is called
Gate Arrays.
- Able to implement feeding back the outputs to and array for improved functionality.
- Available with 3-state outputs (1, 0, high impendence) which are controlled by input, OE.

(1) OE=0 output = open (which can be used to drive the pin as an input which is why
sometime 3-state pins are referred to as I/O)
(2) OE=1 output = input

A
1
A
0

p
0

p
1

F
0

Digital Logic Design Page 91

PALs or GALs are named based on the number of inputs and outputs (PALxxyzz) where:

xx is the number of maximum AND array inputs
y represent the type of output
- Combination output: H is active High, L is active low, P is programmable
- Registered outputs: R is registered (Contains memory devices), RP is registered
with programmable polarity.
- Versatile: V indicates programmable output macro-cells which can be configured to
be either combinational or registered.
zz represents the maximum number of dedicated outputs.

For example: PAL16L8 is active-Low output with 16 inputs and 8 outputs.

PALs and GALs are programmed using Universal programmers which use JEDEC fuse map
file format. Some of the other names commonly used to refer to these devices based on their
complexity or size are:

Simple Programmable Logic Devices (SPLD)

Complex Programmable Logic Devices (CPLD)

PAL usage example: Implement F(A
0
,A
1
)=
1 0 1 0
. . A A A A +
Here again only one Fuse map is needed (AND array connection). Also need to consider if
there are any terms that can be shared. In this case we do not have any shared terms.
A
n
A
0

p
0

p
1

p
(2
n+1
-1)

n-bit input
Programmable AND array
. . .
p
(2
n+1
)

OE
0

OE
1

. .
Factory set
Intact Fuse
Digital Logic Design Page 92

Benefits of PLDs over individual gates:
- Shorter design time (rapid prototype).
- Allow for rapid design changes.
- Decreased PC board real estate.
- Improved reliability since they require fewer packages and interconnections.

Signal Polarity Convention
There are two types of convention: Positive Logic Convention (PLC) and Direct Polarity Indication
(DPI). It is recommended that polarity be consistent unless there is a practical reason to change
polarity.

Positive Logic Convention (PLC)
- Other name for PLC: True Form.
- PLC has been used so far and we will continue to use it in the rest of the text. It is best
suited for working with logic (ones and zeros).

Direct Polarity Indication (DPI)
- Other name for DPI: Complemented Form.
- DPI is also referred to as the mixed signal since each signal can have polarity attached to it
For example W(H) is W in positive logic which is the same as ) (L W
- DPI is preferred by engineers who need to be aware of voltage levels correlating with the
active levels
- Here is a comparison of DPI and PLC signal naming

PLC Signal Name DPI signal Name Type of Signal
A
A(H) or ) (L A
Active High
A ) (H A or A(L)
Active Low
Use bubble o to indicate
negation
Use wedge to indicate
polarity (Low)

Write signal name with no
over bar and change to
Active low with polarity
indicator.


(1) Double complementation can be used to write equivalent signal names in a number of
formats
A
1
A
0

p
0

p
1

OE0
Fuse Map
F(A
0
,A
1
)
Digital Logic Design Page 93
(a) ) ( ) ( ) ( ) ( L A H A L A H A A = = = =
(b) ) ( ) ( ) ( ) ( L A H A H A H A A = = = =


(2) To fully specify a circuit, you need to provide a Signal List (SL) in addition to function. If
the SL is not provided, then it will be assumed to be positive logic.
(a) PLC F=A.B + C.D; SL: D C B A F , , , ,
(b) DPI F=A.B + C.D; SL: F(H), A(H), B(L), C(L), D(H)

Digital Logic Design Page 94
3.10. Additional Resources

Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 6 Combinational Logic Design Practices
Digital Logic Design Page 95
3.11. Problems
Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.

Digital Logic Design Page 96
Chapter 4. Introduction to Feedback Circuits and Sequential Logic Analysis

This is the first section in Sequential Logic Design and Analysis.

4.1. Key concepts and Overview
SR flip-flops
Asynchronous Sequential Logic Issues
Finite State Machines (Sequential Logic Circuits)
Additional Flip-Flop Circuits
Sequential Circuit Analysis
Debouncing Switches
Additional Resources
Problems
Digital Logic Design Page 97
4.2. SR Flip-Flops
SR flip-flops are the simplest form of single-bit memory (latch). A Latch is also known as a bi-stable
memory device. Flip-flop is used to store value of input.

SR flip-flops have set and reset inputs. The circuit for a SR flip-flop is shown below:

Q
+
is used to refer to the next output state when the current output state is Q
Unlike combinational logic, sequential logic Q
+
is dependent on the value of previous output Q.
Q
+
(S, R, Q) = R Q S + +
Note: Q
+
is dependent on inputs S and R as well as current state, q.



Present-State/Next-State (PS/NS) Table
The PS/NS table is the sequential circuit equivalent to combinational circuits truth table. As it can be
seen from the following example, instead of output, PS/NS table has current and next state:

Present External
State(PS) Input Signal
Q S R
Next State
(NS)
Q
+
Comment


Additional Comment
0 0 0 0 hold 0 Q is stable , Q
new
= Q
0 0 1 0 hold 0 Q is stable , Q
new
= Q
0 1 0 1 set Q is unstable, Q
new
= Q+ after t =Q
0 1 1 0 normally not allowed Q is stable , Q
new
= Q, reset dominant
1 0 0 1 hold 1 Q is stable , Q
new
= Q
1 0 1 0 reset Q is unstable, Q
new
= Q+ after t =Q
1 1 0 1 hold 1 Q is stable , Q
new
= Q
1 1 1 0 normally not allowed
Q is unstable , Q
new
= Q+ after t =Q,
reset dominant


Compressed Characteristic Table
Compressed Characteristic Table is another way to describe sequential circuit that is simpler to
generate than PS/NS table while provide most of the information required. Compressed
Characteristic table is commonly used in sequential circuit design and analysis. Below is an example
of Compressed Characteristic table for SR flip-flop.

t
(delay)
Q
Q
+

R
S
R Q S Q + + =
+

Characteristic equation
Feedback signal, Q
Feed Forward Signal
Q S +
Digital Logic Design Page 98


K-map for flip-flops
K-maps can be generated based on flip-flops PS/NS table. The following K-map is for a SR flip-flop.

Note:
Minterms 3, 4 and 7 are unstable and shown on K-map without an underlined. As stated earlier,
unstable state will change after the t delay.

0 1
0 0
0 0
1 1
SR
Q
00
01
11
10
0 1
Q
+
(S,R,Q) = R S R Q . . +
S R Q+

0 0 Q
0 1 0
1 0 1
1 1 0 (reset dominant)
Digital Logic Design Page 99
4.3. Asynchronous Sequential Logic Issues
A circuit that uses latches (flip-flops) but does not use a clock to synchronize all signals is called
Asynchronous Sequential Logic. Here we will explore the issues that may be present in asynchronous
design.

Race Condition
For example (SR flip-flop)
S R Q = 000
S changes to 1 S R Q = 100 (unstable or transitory state) Q
+
= 1 (refer to table)
S R Q = 101 (after delay) A stable state. This state will be maintained until the External input
changes.



If the S and R inputs change quickly (one after another) before the output settles into a new
stable state, the input provides a race condition (each trying to change the output first). If the
output becomes a predictable stable state, then the race is non-critical.

A critical race occurs if the circuit output ends in an unpredictable stable state.

Example of a Critical Race
S R Q = 110
SR are changed simultaneously to 00
- S may change first S R Q = 010 Q+ = 0 Stable state
next R changes, SRQ = 0 0 0 Q+ = 0 Stable state


- R may change first S R Q = 100 Q+ = 1 Unstable state
next S changes, SRQ = 0 0 1 Q+ = 1 Stable state

1
0 1
0 0
0 0
1
SR
Q
00
01
11
10
0 1
0 1
0 0
0 0
1 1
SR
Q
00
01
11
10
0 1
Digital Logic Design Page 100

Note that depending on if S changed first (case 1) or R changed the first (Case 2), final state
will be different, which means we have a critical race.

To insure proper operation of well-designed asynchronous sequential logic circuits (no critical
race), allow only one external input signal to change at a time. This mode of operation is referred
to as fundamental operating mode.

Transient, Meta-Stable State or Unstable Equilibrium State Output
This is another failure mode of latch circuits which causes the output to oscillate between 1 and 0 and
the final state may be unpredictable.
The cause may be:
Runt pulses
If two inputs feeding a gate are changed nearly simultaneously, a runt pulse may be
produced at the output of the gate.
Positive runt pulse
A positive-going pulse that begins with a value of 0 but doesnt achieve the value of 1
Negative runt pulse
A negative-going pulse that begins with a value of 1 but doesnt achieve the value of 0

1
0 1
0 0
0 0
1
SR
Q
00
01
11
10
0 1
Digital Logic Design Page 101
4.4. Finite State machine
State Diagram
A state diagram is a graphical method of showing each state and the movement to other steps based
on the new values of external inputs. Here are the steps (example for SR flip-flop):


Finite State Machine or Simple State Machine is used to describe a sequential logic circuit

A completely specified state machine is one for which all input conditions are used to specify
each next state condition. For a completely specified machine, the sum = 1 rule applies which
says that all outgoing conditions from a state must sum up to 1.

For example for state 0 of the SR flip-flop, a completely specified state machine, the outgoing
conditions sums up to 0
Sum of Outgoing Conditions 1 . ) ( = + + = R S R S

An incompletely specified state machine is one which is missing some input condition. You may
interpret them as dont care conditions.

Note: For the incompletely specified state machine, the sum of outgoing conditions of all states
are not equal to 1.

Algorithmic State Machine (ASM) Chart
An ASM chart is similar to the programming flow chart and is an equivalent of the state diagram used
to describe a sequential logic circuit (or Finite State Machine).

The chart uses three symbols:

Rectangle is the state box (equivalent to circles in state diagram)

Diamond is the decision box (equivalent to inputs next to the lines in state diagram)
one of two paths provide the exit from decision box:

S R Q+

0 0 Q
0 1 0
1 0 1
1 1 0
(reset dominant)
Step 1. Write the
Compressed
Characteristic Table
Step 2. Present State
/Next State (PS/NS)
Table
S R Q Q+

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
Step 3. Draw a circle for each state
(one output, Q, so 2 state)
Step 4. Draw arrow showing change
for each possible input in each state.
Q=0
Q=1
Hold 0
S R
0 0
0 1
1 1
R S + =
Reset
S R
1 1
0 1
=R
Hold 1
S R
0 0
1 0
R =
Set
S R
1 0
R S. =
Digital Logic Design Page 102
- If condition is true, T or 1 path is taken
- If condition is false, F or 0 path is taken

Oval shape is used for start, end and output box

Example - Below is an ASM Chart example for a SR flip-flop derived from the state diagram:
- State exit conditions are the decision conditions in ASM.
- Emphasis is on state changes. All conditions that do not change the stay are not shown
on the ASM chart.


Timing Diagram
Another tool for describing the functionality of a sequential logic circuit is the timing diagram.
Although the timing diagram is not as scalable as State diagrams or ASM chart, it provides the timing
relationship between input and out signals.

Basic definitions used in timing diagrams
Timing Events
External input changes that cause changes in the output of a sequential logic circuit are
called timing events.
Rise Time (t
PLH
)
The time it takes for a signal to go from a 10% to 90% value (an ideal timing diagram
assumes 0 seconds)
Fall Time (t
PHL
)
The time it takes for a signal to go from a 90% to 10% value (an ideal timing diagram
assumes 0 seconds)
Pulse Width
The time it takes for a signal to go from a 50% value on the rising edge to 50% value on the
falling edge.
Average Propagation delay
In order to simplify a timing diagram, gate delays may be represented by an average
propagation delay t
p
where t
p
=( t
PHL
+ t
PLH
)/2
(an ideal timing diagram assumes 0 seconds)
Q=0
Q=1
R S.
R
True False
False
The advantage of ASM is that it has two outputs
from each decision so it is clear if both conditions
are addressed and therefore the state machine is
completely specified.
True
Digital Logic Design Page 103


An ideal timing diagram for an SR flip-flop
SR flip-flop discussed so far is an asynchronous sequential logic circuit since this latch circuit does
not rely on a system clock for synchronization.


Note: This is an ideal timing diagram where propagation delays are not shown.

Design of Asynchronous Sequential Logic Circuit
Asynchronous Circuit does not rely on a clock which means that hazards may be a design problem.

A couple of rules to avoid logic hazards and critical races:
Rule 1 One external input signal change at a time (fundamental mode)
Rule 2 Before the next external signal is allowed to change, the circuit must be given time
to reach a new stable state. (The circuit path with the longest delay dictates the speed of the
circuit.)

Q
R
S
Timing event

State time
(time between events)
1 2 3
90%
50%
10%
Pulse Width
t
PLH

t
PHL

Digital Logic Design Page 104
Applying the Design Steps to an SR flip-flop

Note: This circuit encounters a critical race condition when SR transitions from 11 to 00.

Designing a Clock Circuit (another simple asynchronous sequential logic circuit)
Start with state diagram

Flow the design process

Timing Diagram

You can increase the period T by one of the following methods:
- Adding to t (more buffer)
- Adding more NOT gates (must be an odd number of gates)
- Adding an RC circuit and adjusting the time constant

Timing Event 1 2 3 4 5
Clock (CLK)
Propagation Delay, t
p
= Not Gate delay + t

Period T = 2t
p
Frequency f = 1/T=1/(2t
p
)
Duty Cycle DC = t
p
/T = t
p
/(2t
p
) = = 50%

T
t
p

Q+ = Q
Step 1. Write the
Compressed
Characteristic Table
Step 2. Draw
Compress K-map
Step 3. Draw the schematic
(since Q is used for Q+, we need a delay element)
Q

t
(delay)
Q
+

Q=CLK
Q=0
Q=1
S R Q+

0 0 Q
0 1 0
1 0 1
1 1 0
Step 1. Write the
compressed
characteristic table
Step 2. Draw the
compressed K-map
Step 3. Draw the schematic
(since Q is used for Q+, we need a delay element)
0 0 1 Q
SR
00 01 11 10
R S Q
R S R Q Q
+ + =
+ =
+
) (
. .

Apply DeMorgans
Theorem twice.
t
(delay)
Q
+

R
S
Q
Q
Since Q and Q are provided, it is call a double-rail
output. If Q was the only output, then it would be
called a single-rail output.
Digital Logic Design Page 105
In practice, most designs use crystal oscillators which oscillate at a precise frequency, providing
more reliable system clock.

Design of Gated Sequential Logic Circuit
Providing another input which controls when the inputs can affect the outputs (latching the inputs)
increases the functionality of the latch circuit. The resulting circuit is called a latched or gated circuit.

Gated Circuit Types
Latches may be classified based on their input control types:

Level activated: Latches input when the control is at a given logic level (High or Low
depending on design)
Edge Trigger: Latches input when the control changes level (rising- or falling-edge,
depending on design)
Pulse-triggered: Latches input when the control is pulsed (a rising-edge followed by a falling-
edge)

Gated S-R flip-flop (latch) Circuit


This circuit allows inputs to affect the outputs only when C=1. When C=0, the latch holds the
last state value at its output. This is an example of high-level activated SR flip-flop.
t
(delay)
Q
+

R
S
Q
Q
(Not always shown)
C
S

C

R
Q

Q
Block Diagram
Gated SR Latch Using NOR gates
Digital Logic Design Page 106
The state diagram showing the effect of Latch Control (C) on the state change.

Note: This circuit, like the SR Latch Circuit, has a critical race when CSR transitions from
111 to CSR=100. To prevent this issue, it is possible not to allow CSR=111.

Q=0
Q=1
Hold 0
C S R
1 0 0
1 0 1
1 1 1
0 0 0
0 0 1
0 1 0
0 1 0

Reset
C S R
1 1 1
1 0 1
Hold 1
C S R
1 0 0
1 1 0
0 0 0
0 0 1
0 1 0
0 1 0
Set
C S R
1 1 0
When C=0, there is no state change
Q=0
Q=1
C.S.R
C + S +R
C.R
C+R
* Another form of State Diagram for the same circuit is shown below:
Digital Logic Design Page 107
4.5. Additional Flip Flops
D flip-flop (or D-latch)
Although we have talked about SR flip-flop first, there are many other types of flip flops. Each have
their own set of advantages and disadvantages. D flip-flop is the most commonly used flip-flops due
to its simplicity. Additionally, D flip-flop does not have an inherent critical race.

SR flip-flops can be modified using NAND gates to create a D flip flop as shown in the following
diagram:

The D flip-flop may be referred to as gated D Latch, a transparent D latch, a level sensitive flip-flop
or data flip-flop. Symbol and Compressed Characteristic table is shown below:


Note: When C=0 (inactive), the last value of D is driving the output. Also it can be shown that it does
not contain critical race and is logic hazard free.

Explore the specifications for 74LS373 level activated and 74LS374 Positive-edge
triggered. Refer to Course Website for the complete specifications including:

- Set up time (t
su
)
- Hold time (t
h
)
- Sampling interval, t
si
= (t
su
+ t
h
)
The Minimum t
si
is required for proper operation of the circuit.
- 3-state output.

Although there are pulse, level activated flip flop and edge-triggered D latches, it is recommended
that new design use edge-triggered flip-flops.

Basic edge-triggered flip-flop
One ways to create a narrow pulse is by using the following circuit:

D flip-flop Symbol
D

C
Q

Q
C D Q+
0 0 Q
0 1 Q
1 0 0
1 1 1
Compressed Characteristic
Table
Q=0
Q=1
C.D
C + D
C.D
C +D
State Diagram
t
(delay)
Q
Q
Q
+

Enable Control,
C
D set
reset
Digital Logic Design Page 108

So you can use this design to implement a positive-edge-triggered D flip-flop circuit with
preset and clear inputs.

t
(delay)
Q
Q
Q
+

C
D
(Clear)
(PreSet)
Circuit Diagram
X
Y
Z
X
Y
Z
t
p
t
p

A pulse is generated only during the rising edge
Digital Logic Design Page 109
Symbols

Application: using D flip-flops with clear to build a shift register

Edge-Triggered and Pulse-Triggered Flip Flop Comparison
A pulse enable the input to change the output. The pulse can be negative or positive
depending on the flip-flop design. Here is a comparison of hold time requirement for positive-
edge and positive-pulse triggered flip-flop.


- A pulse-triggered flip-flop has much longer sampling interval than an edge-triggered flip-
flops; therefore, all new designs use Edge-triggered flip-flops to improve speed.

C
Positive-Edge
Triggered flip-
C
Positive-Pulse
Triggered flip-
t
w
=

t
h

t
su


t
h

t
si

t
s
= Set up time
t
h
= Hold time
t
w
= Pulse width
t
si
= Sampling interval = t
su
+ t
h


Shaded area is the area where
data must be stable.
D1 Q1

CLK

Clear
D2 Q2

CLK

Clear
D3 Q3

CLK

Clear
D4 Q4

CLK

Clear
CLOCK
Vcc
b0 (LSB) b3 (MSB) b1 b2
Data
GND
CLK
DATA
1D

C1
Q
Q
Q
Q
Positive-Edge-Triggered D Flip-Flop
(triangle called dynamic indicator)

CLK
DATA
1D

C1
Q
Q
Q
Q
Negative-Edge-Triggered D Flip-Flop
(Bubbled triangle indicator)
Digital Logic Design Page 110
- A pulse-triggered flip-flop is also called master-salve due to its implementation which
require two D-type flip-flop in a master-salve set up as shown below:


The D flip-flop is the most commonly used bi-stable memory device. The other two kinds used are J-K
and T flip-flops.

J-K Flip Flops
Below is a negative-edge triggered JK flip flop. As in other flip-flops, the inputs J and K are called
excitation inputs.


S

1J

C1

1K

R
PRE

J

CLK

K

CLR
Q



Q
J K Q
+
Comment
0 0 Q no change
0 1 0 reset condition
1 0 1 set condition
1 1 Q toggle
Symbol
Characteristic equation: Q
+
= J.Q + K.Q
Characteristic Table

Q
D


C
S

D


C

R

C
D
Q
Q
Q
Set
Reset
or
S

D


C

R

Q
Q
Set
D
C
Reset
Postponed output symbol
Digital Logic Design Page 111
Toggle or T Flip Flops


Using a JK flip-flop to implement a negative-edge-triggered T flip-flop:


Using D flip-flop to implement a positive-edge-triggered T flip-flop:




1D

C1



D=Q
+

Q



Q
T

CLK
S

1J

C1

1K

R
PRE

T

CLK



CLR
Q



Q
J=K=T Q
+
Comment
0 0 0 Q no Change
0 1 Invalid
1 0 Invalid
1 1 1 Q toggle
Symbol
S

1T

C1



R
PRE

T

CLK



CLR
Q



Q
T Q
+
Comment
0 Q no Change
1 Q toggle
Symbol
Characteristic equation: Q
+
= T.Q + T.Q
Characteristic Table
Digital Logic Design Page 112
4.6. Sequential Circuit Analysis
Flip-flops may be used to design circuits with feedback, such as counters, shift registers, sequence
detectors and controllers.

Feedback systems are classified as synchronous when all changes are synchronized with the system
clock. Feedback systems that do not use the system clock and change as the input change are called
asynchronous.

Synchronous systems are preferred over asynchronous systems since they will not have hazards and
other synchronization issues.

Synchronous systems are also referred to as synchronous finite state machines (FSM).

A FSM utilizes a system clock that adheres to the following definitions:
* Each period of system clock represents a State-Time
* A state represents the state of the flip-flop outputs (value of outputs)
* Synchronous external inputs Xs
* Current machine state, flip-flop outputs Ys
* Synchronous state machine external outputs Zs

Synchronous state machines may be implemented in one of three models based on the characteristic of
its output (Moore, Mealy or mixed-type synchronous state machine):

Moore-type Synchronous Finite State Machine
outputs are a function of the state of the machine Z1(Y1, Y2, Y3)

A Binary counter is a good example of Moore machine since the output of the flip-flops can be
used to represent the count.


Mealy-type Synchronous Finite State Machine
Outputs are a function of the state of the machine and external inputs. Z1 (Y1, Y2, X1, X2, )
Excitation
Forming Logic
(Combinational)
Flip Flops

Input
Output

Clock
System
Clock
External
Inputs (Xs)
Moore output
Forming Logic
(Combinational)
Moore
External Output
Zs(Ys)
Ys
Excitation
input
Feedback
Digital Logic Design Page 113


Mixed-type Synchronous Finite State Machine
Some outputs are Mealy-type and others are Moore-type.

Analyzing Synchronous Systems (General)
There are five steps in analysis of this type of circuit:

1) Assign a present state variable to each flip flop in the synchronous system.
Yi represents flip-flop outputs for i = 1, 2, 3,

2) Write the excitation-input equation for each of the flip-flops and the external-output
(Moore and/or mealy equations). After completing this step, Di, Ji Ki, Ti should be
defined where i=1, 2, 3 {# of flip-flops used}.

3) Substitute the excitation input equation into the characteristic equations of the flip-
flops to obtain the next state equations.
For D flip-flops Yi
+
= Di for i=1, 2, 3,
For J-K flip-flops Yi
+
= Ji.Yi + Ki.Yi for i=1, 2, 3,
For T flip-flops Yi
+
= Ti <XOR> Yi for i=1, 2, 3,

4) Obtain a PS/NS table or a composite K-map using the next state and external-out
(Mealy and/or Moore) equations. Separate K-maps can be used for the external
Excitation
Forming Logic
(Combinational)
Flip Flops

Input
Output

Clock
System
Clock
External
Inputs (Xs)
Mealy
External Output
Zs(Ys, Xs)
Ys
Excitation
input
Feedback
Mealy Output
Forming Logic
(Combinational)
Moore Output
Forming Logic
(Combinational)
Moore
External Output
Zs(Ys)
Excitation
Forming Logic
(Combinational)
Flip Flops

Input
Output

Clock
System
Clock
External
Inputs (Xs)
Mealy
External Output
Zs(Ys, Xs)
Ys
Excitation
input
Feedback
Mealy Output
Forming Logic
(Combinational)
Digital Logic Design Page 114
outputs if desired.

5) Use the PS/NS table or the composite K-map to obtain a state diagram, ASM chart or
timing diagram to show the behavior of the circuit.

Apply the five step analysis technique to the following circuit:

Note: This is a Mealy-type machine since the output depends on external input and flip-flop outputs.


1) Assign a present state variable to each flip flop in the synchronous system.
Yi representing flip-flop outputs for i = 1, 2, 3,
Solution: Refer to the schematics

2) Write the excitation-input equation for the flip-flops and the equation for the external-output
(Moore and/or mealy equations). After this step is completed, the values of Di, Z should be
defined for all flip-flops.

Solutions:
D1 = X.Y1.Y2
D2 = Y1.Y2 + X
Z = Y1.Y2.X

3) Substitute the excitation-input equation into the characteristic equations for the flip-flops to
obtain the next state equations.

D flip-flops Yi
+
= Di for i=1, 2, 3,

Solutions:
Y1
+
= D1 = X.Y1.Y2
Y2
+
= D2 = Y1.Y2 + X

4) Obtain a PS/NS table or a composite K-map using the next state and external-output (Mealy
and/or Moore) equations. Separate K-maps can be used for the external outputs if desired.
Solutions:
X
D1

C1
D2

C2
System
Clock
Q1
Q2
Q2
Q1
Z
Y1
Y2
Digital Logic Design Page 115


5) Use the PS/NS table or the composite K-map to obtain a state diagram, ASM chart or timing
diagram to show the behavior of the circuit.

Solutions:
Since there are two flip-flop, the state machine has 4 states.

00
01
10
11
Classic State machine
* Links show input, output in 1s and 0s
* State is inside the circles

In the case of Moore machines, outputs must be inside the circle because they only depends on
the current state.

Note: A simplified State machine shows the links between states in Boolean expressions.
1,0
1,0
1,1
0,0
0,0
1,0
0,0
Notes
1) State 00 is reset

2) Output Z=1 only when the input
sequence is 101, so this could be
101 pattern detector.

3) State 10 is referred to as
illegal state, unused state or an
unreachable state.

4) One way to ensure you dont end
up in illegal state is to have a power
on reset.
Y
1
Y
2

X,Z
Legend
0,0
Y1 Y2 X Y1
+
Y2
+
Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1
PS/NS Table Composite K-map where:
Ys and Xs are independent variables
Ys
+
and Zs are Dependent
OR
00,0 01,0
11,0 01,0
00,0 01,1
00,0 01,0
Y
1
+
Y
2
+
, Z
X
Y
1
Y
2

00
01
11
10
0 1
Digital Logic Design Page 116
An alternative method is the use of Algorithmic State Machine (ASM) chart to describe the functionality.


Analysis of JK Flip-Flop Circuits
Apply the 5-step FSM analysis to the following circuits:


1) Assign a present state variable to each flip flop in the synchronous system.
Yi representing flip-flop outputs for i = 1, 2, 3,
Solution: Refer to the schematics

2) Write the Excitation-input equation for JK flip-flop and the equation for the external-output.






3) Substitute the excitation-input equation into the characteristic equations for the flip-flops to
obtain the next state equations.
For J-K flip-flops Y
i
+
= J
i
.Y
i
+ K
i
.Y
i
for i=1, 2, 3,

J
1
Q
1


K
1
Q
1

C
1

System
Clock
J
2
Q
2


K
2
Q
2

C
2

Z
X
Y
1
Y
2

00
X
01
X
11
X
10
X
(illegal
State)
(Reset
State)
0
0
0
0
1
1
1
1
Z
Mealy Output
Note: When Z is not shown, it is assumed the output is 0.
Digital Logic Design Page 117
Y
1
+
=

Y
2
+
=


4) Obtain a PS/NS table.

5) Use the PS/NS table or the composite K-map to obtain a state diagram to show the behavior
of the circuit.















Input Date Synchronization
Synchronized systems have to accept external-inputs that may not be synchronized with the system
clock. Typically, an input is synchronized with the rising or falling edge of the system clock prior to
using it in the system:

In-Phase Synchronization is when the input is synchronized with the rising edge of the system
clock.
Anti-Phase Synchronization is when the input is synchronized with the falling edge of the system
clock.

Rising
Edge
Falling
Edge
Y
1
Y
2
X Y
1
+
Y
2
+
Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
PS/NS Table
Digital Logic Design Page 118
4.7. Debouncing Mechanical Switches
Mechanical switches bounce for a few milliseconds before stabilizing in their new position. Meaning, the
switch will open and close repeatedly (bounce) when switch is changed to closed position. If the switch is
used as an event or an input where each transition is considered a new input then the designer is
required to debounce the switch before using the switch value in the rest of the system.

There are numerous approaches to debouncing a switch output. Here are four typical approaches to
debouncing:

RC Circuit Debounce
The most basic approach is to use a Resistor and Capacitor (RC) circuit to debounce switches. This
method uses the time constant ) ( RC = t to slow the circuit eliminating the bounce. R and C value
will be selected based on duration of switch bounce. Here is the simplest form:


The drawback of this approach is that Out transition from low to high may be too slow for use in
digital circuits.

Flip Flop Design
SR Flip Flop Variation
This method uses a variation of SR Flip Flop to debounce a switch output as shown below:


+5V
GND
A
B
Out
Vcc
GND
Out
Digital Logic Design Page 119


D Flip Flop with Set & Reset
This approach uses a D Flip Flop with Set and Clear to debounce the switch output as shown
below



Software Debounce
In systems with microprocessor, it may be advantages to programmatically debounce the switch.
This is done by reading the value of switch over a period of time that is longer than debounce time for
the switch. The read value will be accepted only if the value is the same across two or more reading.




Set Q

Clear

D Clock
Vcc
GND
Out
Switch in
Position A
Change Switch
to Position B
Change Switch
to Position A
A
B
Out
Digital Logic Design Page 120
4.8. Additional Resources

Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 7 Sequential Logic Design Principles
Digital Logic Design Page 121
4.9. Problems
Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.

Digital Logic Design Page 122
Chapter 5. Sequential Circuit Design & Techniques

5.1. Key concepts and Overview
Synchronous Finite State Machine Design (Classical Technique and Examples)
State Assignment Encoding, Shift Register Counters, and Enable Inputs
Inspection Design Methods for Finite State Machines (Inspection Techniques)
Additional Resources
Problems
Digital Logic Design Page 123
5.2. Synchronous Finite State Machine Design (Classical Design)
Common Examples of Synchronous FSM
Up and Down Binary Counters
Shift Registers
Sequence Detectors
Controllers

The Seven-Step Design Process for Synchronous Sequential Design (Classical Design)

1) Organizing the Design Specifications Use one or more of the following tools:
System Diagram, Timing Diagram, State Diagram or ASM Chart.

2) Determine the number of flip-flops based on the number of states
At this point, designer may choose to design a full encoding or one-hot encoding. Full
encoding utilize all possible combinations of the flip-flops and the following inequality is used
to decide the number of flip-flops:
2
#flip-flop
# States

The other encoding option is one-hot encoding where state is defined by which flip-flops
output is 1. So the number of flip-flop is equal to the number of States.

Once the number of flip-flops is determined, assign one variable for each of the flip-flop
output.

3) Assign a unique code to each state (a specific value for present state variables)

4) Select the flip-flop type to be used, draw the Present State/Next State (PS/NS) table,
determine the excitation input equations and the Moore and/or Mealy output equations.

Remember the excitation input and next state relationship flip-flops:

Y K Y J Y or
Y K
Y J
Flop Flip JK
Y T Y or Y Y T Flop Flip T
D Y or Y D Flop Flip D
. .. + =
=
=

= =
= =
+
+
+
+ +
+ +

Note: D flip-flops are generally preferred for most synchronous sequential designs.

5) Draw the circuit schematic (paper or CAD tool).

6) Perform a simulation to test the functionally of the design.

7) Implement the design with hardware.


Digital Logic Design Page 124
EXAMPLE - Design a 2-bit binary up-counter with a ripple carry output (RCO) using D flip-flops. The
input CLR is an asynchronous input that overrides the clock.
Step1) Design specifications using a timing diagram
**Notes:
1) T
clk
is the clock period and ST is the state time.
2) The first two events are less and then more than T
clk.

3) Y1Y2 are the states (counts).
4) RCO is a Moore output indicating when the maximum count has been reached.

For completeness, we can also show the state diagrams. Although a timing diagram is more complete,
the state diagram is simpler to understand, since it does not contain the clock timing information.


Another way to show the functionality of this circuit is to use a PS/NS table.
Note: The Next state, NS is the estate of the machine during the next clock cycle.
a
00, RCO
d
11, RCO
b
01, RCO
c
10, RCO
State = Y
1
Y
2
,
Z

CLR
CLK
CLR
Y1 (msb)
Y2 (lsb)
RCO
a
ST > T
clk

c
ST < T
clk

Asynchronous Reset
b
ST = T
clk

c
ST = T
clk

d
ST = T
clk

a
ST = T
clk

b
ST = T
clk

Timing Events 1 2 3 4 5 6 7 8 9
Digital Logic Design Page 125


Step 2) Determine the number of flip-flop based on the number of states.
For full encoding (#states = 4) 2
(#flip-flop = 2)
.

Step 3) Assign Unique code to each state.
Already done in the state diagram.

Step 4) Write the excitation-input equations
The D flip-flop excitation equation is D = Y
+
.

All we need is the K-map for each of the desired outputs Y
1
+
,Y
2
+
, RCO:

0 1 0
0
1
0
1
00
01
11
10
Y1Y2
D1 = Y1
+

D1 = Y1.Y2 + Y1.Y2
D1 = Y1
XOR
Y2
1
0
0
1
00
01
11
10
Y1Y2
D2 = Y2
+

D2 = Y2
0
0
1
0
00
01
11
10
Y1Y2
RCO
D2 = Y1.Y2
Excitation-inputs and output RCO equations
derived from separate K maps
(These equations are also called design equations)
00
01
11
10
1 0 0
0 0 1
1 1 0
A composite K-map is a short
hand for multiple K-maps.
Y1Y2 Y1
+
Y2
+
RCO
Asynchronous Present Next Present
Clear Input State State Output
CLR Y1 Y2 Y1
+
Y2
+
RCO
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 0 0 1
0 X X 0 0 0
Present State / Next State (PS/NS) Table
Present Next Present
State State Output
Y1 Y2 Y1
+
Y2
+
RCO
0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 0 0 1
Simplified PS/NS Table
(Note: CLR=0 Y1Y2=00)
Digital Logic Design Page 126
Step 5) Draw the Circuit Schematic.
Steps 6 & 7) Testing and hardware implementation will be skipped for this example.

A Second Application of the Classical Design Process:
Design a synchronous sequential circuit called Div-by-3, having an output Z that divides the system
clock frequency f
CLK
by 3. The output duty cycle of two-thirds (2 CLK cycle high, 1 cycle low). Design
the circuit using positive-edge-triggered flip-flops.

Step1) Design Specifications Using a Timing Diagram

Step 2) Determine the number of flip-flop based on the number of State
(# state = 3) 2
(#flip-flop = 2)
Assuming Full Coding

Step 3) Assign a unique code to each state
a: 00, b:01; C:11

Step 4) Write the excitation-input equations
The D flip flop excitation equation is D = Y
+
CLK
CLR
Z (output)
Y1(msb)
a
ST = T
clk

b
ST = T
clk

c
ST = T
clk

a
ST = T
clk

b
ST = T
clk

Timing Events 1 2 3 4 5 6 7
b
ST = T
clk

1 T
clk

2 T
clk

Y2
D1
Q1
CLK
Q1
R1
D2
Q2
CLK
Q2
R2
CLR
SYS CLK
RCO
Y1
Y2
Y2
D1
D2
Digital Logic Design Page 127
All we need is the composite K-map for each of the desired outputs Y1
+
,Y2
+
, Z:


Step 5) Draw the Circuit Schematic

A third application of the classical design process (using T flip-flop):
Design a synchronous sequential circuit identical to the previous example, except implement the
design using T flip-flops instead of D flip-flops.

Step1) Design Specifications using a Timing Diagram
1D
Q
CLK
Q
R
1D
Q
CLK
Q
R
CLR
SYS CLK
Y1
Y2
Y2
D1
D2
Z
Y1
0 1 1
00
01
11
10
1 1 1
0 0 0
- - -
- means dont care
Y1Y2 Y1
+
Y2
+
Z
D1 = Y1+ = Y1.Y2
D2 =Y2+ = Y1
Z = Y1
10 State is never reached.
Digital Logic Design Page 128

Step 2) Determine the number of flip-flop based on the number of State
(#state = 3) 2
(#flip-flop = 2)
Assuming Full Coding

Step 3) Assign a Unique code to each state
a: 00, b:01; C:11

Step 4) Write the excitation-input equations:
The T flip-flop excitation and characteristic equations are Y
+
= T
XOR
Y and T = Y
+

XOR
Y
Note: You may derive general excitation equation from re-arranging the characteristic table
for the Tflip flop to obtain the excitation table for the T flip-flop as shown below:


Write the PS/NS table (for T & JK, this intermediate step is helpful)
Y
1
Y
2
Y
1
+
Y
2
+
T
1
T
2
Z
0 0 0 1 0 1 0
0 1 1 1 1 0 1
1 1 0 0 1 1 1
1 0 - - - - -
Unused States
T Y
+
0 Y
1 Y
T Y Y
+
0 0 0
0 1 1
1 0 1
1 1 0
Characteristic
table
Output Excitation
table
Y Y+ T
0 0 0
0 1 1
1 0 1
1 1 0
Input Excitation
table
T = Y
+

XOR
Y
Input Excitation Eq.
CLK
CLR
Z (output)
Y1(msb)
a
ST = T
clk

b
ST = T
clk

c
ST = T
clk

a
ST = T
clk

b
ST = T
clk

Timing Events 1 2 3 4 5 6 7
c
ST = T
clk

1 T
clk

2 T
clk

Y2
Digital Logic Design Page 129
Draw the composite K-map for each of the desired outputs Y1
+
,Y2
+
, Z:


Step 5) Draw the Circuit Schematic


Another Application of the Classical Design Process (using JK flip-flops)
Design a synchronous sequential circuit identical to the previous example, except implement the
design using JK flip-flops.

Step1) Design Specifications Using a Timing Diagram
CLK
CLR
Z (output)
Y1(msb)
a
ST = T
clk

b
ST = T
clk

c
ST = T
clk

a
ST = T
clk

b
ST = T
clk

Timing Events 1 2 3 4 5 6 7
c
ST = T
clk

1 T
clk

2 T
clk

Y2
T1
Q1
CLK
Q1
R1
T2
Q2
CLK
Q2
R2
CLR
SYS CLK
Y1
Y2
Y2
T1
T2
Z
Y1
00
01
11
10
T1 = Y2
T2 = Y1 Y2 + Y1Y2 = Y1
XNOR
Y2
Z= Y1

Note: - means dont care
Y1Y2 T1 T2 Z
0 1 1
1 0 1
1 1 0
- - -
Digital Logic Design Page 130

Step 2) Determine the number of flip-flop based on the number of states
(#states = 3) 2
(#flip-flop = 2)
assuming full encoding.

Step 3) Assign Unique code to each state
a: 00, b:01; C:11

Step 4) Write the excitation-input equations
The JK flip-flop excitation equation is JK Y
+
= J.Y + K.Y
You may derive the general excitation equation from the characteristic table for the JK
flip-flop to obtain the excitation table for the JK flip-flop, as shown below:

Write the PS/NS table for JK, flip-flops (this intermediate step is helpful)

Draw the Composite K-map for each of the desired outputs Y1
+
,Y2
+
, Z:

00
01
11
10
Y1Y2 J1 K1 J2 K2 Z
0 1 1
1 0 1
0 1 0
- - -
0 1
0 1
1 0
- -
J
1
= Y1.Y2
K
1
= Y1 + Y2
J
2
= Y1
K
2
= Y1
Z = Y1
Note: - means dont care
Y
1
Y
2
Y
1
+
Y
2
+
J
1
K
1
J
2
K
2
Z
0 0 0 1 0 1 1 0 0
0 1 1 1 1 0 1 0 1
1 1 0 0 0 1 0 1 1
1 0 - - - - - - -
Unused State
J K Y Y
+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Characteristic
table
Output Excitation
table
Y Y+ J K
0 0 0 -
0 1 1 -
1 0 - 1
1 1 - 0
Input Excitation
table
Note: - = dont care
J = Y
+
K = Y
+

Input-Excitation Eq.
J K Y
+
0 0 Y
0 1 0
1 0 1
1 1 Y
Digital Logic Design Page 131
Step 5) Draw the Circuit Schematic

Step 6) Test (with a test plan)
Step 7) Implement

Determining the Maximum Clock Frequency of a Synchronous State Machine
The maximum clock frequency that a system can handle is driven by the set-up, hold and margin
times required by the flip flops in the synchronous system.

We can see that the clock frequency is limited by f
max
=1/T
CLK(min)
as shown below:

T
CLK(min)
= t
pff(max)
+ t
pcomb(max)
+ t
marg)
+ t
su
+ t
h
where
t
pff(max)
= Maximum propagation delay time through flip-flop from the clock tick to Q output
t
comb(max)
= Maximum propagation delay time through combinational logic
t
marg)
= Margin time, it is always a good design practice to allow for tolerances.
t
su
= Set-up time requirement
t
h
= Hold time requirement

Note: We assume that t
h
+ t
h(marg)
< t
pff(min)
+ t
pcomb(min)


EXAMPLE - Timing
Determine the absolute maximum clock frequency for the divide-by-3 synchronous machine
CLK
T
CLK

(min)

t
pff

(max
)
T
pff

(min)

t
pcomb

(max
)
T
pcomb

(min
)
t
su

(marg
) t
su
t
h
t
h(marg)

INPUT
OUTPUT
1J
1 K Q
CLK
Q
R
1J
1K Q
CLK
Q
R
CLR
SYS CLK
Y1
Y2
Y2
J1
K1
Z
Y1
J2
K2
Digital Logic Design Page 132

74LS08 AND gate
t
pcomb
: Min at 3 ns and Max. at 18 ns
75LS175 D-flip-flop
t
pff
: Min at 0 ns and Max. at 42 ns
t
su
: Min at 20 ns
t
h
: Min at 0 ns
The fastest clock speed
T
CLK(min)
= t
pff(max)
+ t
pcomb(max)
+ t
marg)
+ t
su
= 42 + 18 + 0 + 20 = 80 ns
F
CLK(max)
= 1/T
CLK(min)
= 1/80*10
-9
= 12.5 MHz

12.5 MHz is significantly slower than todays technology, where the average personal
computer clock frequency is many GHz.

Example Design
Design a system (Finite State Machine, FSM) that cycles through the following colors as shown
below:



Red Yellow Blue Black
White Green Violet Cyan
1D
Q
CLK
Q
R
1D
Q
CLK
Q
R
CLR
SYS CLK
Y1
Y2
Y2
D1
D2
Z
Y1
t
pcomb

t
pff

Digital Logic Design Page 133
5.3. State Assignment Encoding, Shift Register Counters, and Adding an Enable Input
Full-encoding compared to one-hot encoding
Full encoding uses all possible combinations of flip flop outputs to represent states, so the
equation 2
#flip-flop
#states is used to determine the number of flip-flops required. Full encoding:

leads to minimum number of Flip Flops.
best used with Simple Programmable Logic Devices (SPLDs) and Complex Programmable
Logic Devices (CPLDs).
One-hot encoding, on the other hand, allows only one flip-flop outputs to be active (or hot) at
any one time. So the equation #flip-flop = #states is used to determine the number of flip-flops
required. One-hot encoding:

leads to larger number of flip-flops.
best used with Field Programmable Gate Arrays (FPGAs). FPGAs, which are sometime
referred to as a sea of flip-flops, has made the use of one-hot encoding a viable approach
due its overabundance of flip-flops.

Power-on Reset Circuit
With either type of encoding there may be illegal and/or unreachable states. Additionally, when your
system is turned on initially or regains power after an interruption, it is important for it to recover in a
predefined state.

A power-on reset circuit ensures that a reset is generated immediately after a power up condition.
This could be used to preset or reset flip flops into the desired state.

Using RC circuits, we can design circuits that generate active high or low signals, depending on our
needs, as shown below:
Digital Logic Design Page 134
Additional Types of Shift Registers:
Parallel in/Parallel out
Parallel in/Serial out
Serial in/Parallel out
Serial in/Serial out

Additional Types of Counters:
Ring Counters; a 1 is shifted through each flip-flop while all the other flip-flop outputs are 0.
(one hot encoding is a recommended design)
Twisted Ring Counters (or switch tail ring counter, Johnson counter, mobius counter)
Linear Feedback Shift Register Counter (or maximum length shift counters)
Depending on design it will count all possible states, but skips all 0s and 1s states.

Recommendation: Reader is encouraged to explore full definition of these counters and others
through independent research.

Adding an Enable Input
It may be necessary to stop the count at times and then continue counting. In this section we will
design a Full-Encoded Stoppable Counter. This counter will count up as long as EN is asserted;
otherwise it will stop the counting.

GND
V
cc
=+5V
Diode
Schmitt
Trigger
Vc CLR CLR
C=10 uF
R=10 K
On
Vcc
Off
5V
Vc
0V
H
CLR
L
H
CLR
L
RC with C grounded
GND
V
cc
=+5V
Vc CLR CLR
C=10 uF
On
Vcc
Off
5V
Vc
0V
H
CLR
L
H
CLR
L
RC with R grounded
R=10 K
Power is off Power is on
Time it takes the Vc = 5(1- e
t/RC
)
to trigger the Schmitt trigger
Time it takes the Vc = 5 (e
t/RC
) to
trigger the Schmitt trigger
Digital Logic Design Page 135
State Diagram for a three-bit (Y
1
Y
2
Y
3
) Full-Encoded Stoppable Counter

Most standard counters such as 74XX160, 74XX161, 74XX162, 74XX163 have similar
designs.
RCO can be used to enable the next counter in the cascade (if one exists) to start counting.

Below is a composite K-map for a 3-bit binary up stoppable counter with enable input EN,
asynchronous clear input CLR, and ripple-carry out RCO.

The flip-flop input excitation equation and RCO output equation can be derived from the composite K-
map or (need 3 flip-flops):

D1=Y1
+
= EN.Y1.Y2.Y3 + Y1.Y2+Y1.Y3+EN.Y1
D2=Y2
+
= EN.Y2.Y3 + Y2.Y3+ EN.Y2
D3=Y3
+
= EN.Y3 + EN.Y3
RCO = Y1.Y2.Y3

This counter can be designed with one-hot encoding using 8 flip flops.

000
001
001
010
011
100
010
011
100
101
101
110
111
000
110
111
000 001 011 010 100 101 111 110
Y
1
Y
2
Y
3

0
1
Note: CLR=1 Y
1
Y
2
Y
3
= 000
0 0 0 0 0 0 1 0
RCO
Y
1
+
Y
2
+
Y
3
+
EN
EN
EN
EN
EN
EN EN
EN
EN
EN
EN
EN
EN EN
EN
EN
EN
000
RCO
001
RCO
010
RCO
011
RCO
100
RCO
101
RCO
110
RCO
111
RCO
Digital Logic Design Page 136
Using Enable in Synchronous circuits
In order to maintain the benefits of a synchronous system (avoiding clock glitches), it is important that
the clock to all of the components be the same (uninterrupted). Here is what NOT TO DO:


Instead, if you need to enable a flip-flop, use one with enable capability designed in or use the MUX
as shown:

Flip-flops with enable allows the designers to focus on the input/output synchronization. Enabled flip-
flops simply require a connection to the enable pin, similar to the Clear and Preset signals.

1D
D
EN

ClK
0
1 S0
1D

1EN

CLK

1D
EN
CLK
D
Digital Logic Design Page 137
5.4. Inspection Design Methods for Finite State Machines
The classical design methods are limited to a small number of inputs, states and outputs since the K-
maps required become too difficult to draw and work with.

The Inspection Design Method provides ways to write the excitation equation for flip-flops by inspection
from a timing diagram, a state diagram, or ASM chart of a synchronous Finite State Machine. By
observing or inspecting the present state (PS) and next state (NS) for each state variable, the D, T and J-
K excitation equations can be written.

The equations derived using inspections are not typically minimum equations. There are two inspection
methods:
Set-Hold 1 Method
or
Clear-Hold 0 Method

Set - Hold 1 Method for obtaining D excitation-input equations
We use the following table to write D excitation equations directly from a state diagram, ASM chart or
timing diagram.

Present State
(PS/NS)
Yi Yi
+


Di

Comment
User for 1s
(Set-Hold 1)
Use for 0s
(Clear-Hold 0)
0 0
0 1
1 0
1 1
0
1
0
1
Hold 0 transition
Set transition
Clear transition
Hold 1 transition

Di

Di
Di

Di


The Set-Hold 1 Method can be used to obtain the D excitation equations for the 1s of each
state variable (flip-flop outputs)
Di = (PS.external input conditions for set) + (PS.external input conditions for hold 1)
for i=1, 2, 3

Note: This method solves for the 1s of the function.

We could also apply the Clear-Hold 0 Method to obtain the D excitation equations for the 0s
of each state variable (flip-flop outputs)
Di = (PS.external input conditions for clear) + (PS.external input conditions for hold 0)
for i=1,2,3,
Note: This method solves for the 0s of the function and it is equivalent to the first method.

For both of the methods, if we have not completely specified FSM meaning and some state
values are dont care, enter them as such so that we can use them in later reduction processes.

Example - Obtaining the D excitation-input equations from a state diagram
Obtain the excitation equations for the following state diagram of a mixed (Mealy-Moore)
machine.

State Y1Y2
Input STOP
Digital Logic Design Page 138
Output Z0 Z1

By observing (or inspecting) all set transitions (Y1 =0 Y1
+
=1) and all Hold 1 transitions
(Y1 =1 Y1
+
=1) we can write the D1 excitation equation from the state diagram:
D1 = Y1.Y2 + Y1.Y2 + Y1.Y2.STOP

Repeat the previous step for D2 using Y2 transitions
By observing (or inspecting) all transitions (Y2 =0 Y2
+
=1) and all Hold 1 transitions (Y2
=1 Y2
+
=1) we can write the D1 excitation equation, from the state diagram:
D2 = Y1.Y2.STOP + Y1.Y2 + Y1.Y2.STOP

Note: We could also look for the 0s function using Clear-hold 0 method to find D1 and D2

Based on the state diagram Z0 is a Moore-type output since it only depends on the state
variables (flip-flop outputs).

We will use a K-map with state variables to find minimized the Z0 equation.

Z1 is a Mealy-type output since it depends on both the state variables and external input
We will use a K-map with state variables plus external input to find minimize Z1 equation

Example - Design a 2-bit up-and-down counter using the inspection design Method.
- Draw system diagram




0 0
0 0
Z0 = Y1.Y2.STOP
STOP
Y1Y2
0

1
00 01 11 10
1 0
0 0
1 0
0 0
Z0 = Y1.Y2
Y1
Y2
0

1
0 1
a
00,Z0
b
01,Z0
c
10,Z0
d
11,Z0
STOP, Z1 STOP, Z1
STOP, Z1
STOP, Z1
Digital Logic Design Page 139


- Draw the Present/Next State Table









- Write the Excitation-Input Equations
Di = E(PS.external input for set) + E(PS.external input for hold 1 )








- Draw the schematics










Set-Clear Method for obtaining T Excitation-Input Equations
The following table will be used to write T excitation equations directly from a state diagram, ASM
chart, or a timing diagram.


Present State
(PS/NS)
Yi Yi
+


Ti

Comment
User for 1s
(Set-Hold 1)
Use for 0s
(Clear-Hold 0)
0 0
0 1
1 0
1 1
0
1
1
0
Hold 0 transition
Set transition
Clear transition
Hold 1 transition

Ti
Ti

Ti


Ti

The Set Clear Method can be used to obtain the T excitation equations for the 1s of each
state variable (flip flop outputs)
Ti = (PS.external input conditions for set) + (PS.external input conditions for clear)
for i = 1,2,3,

Note: This method solves for the 1s of the function.

We could also apply the Hold 0 - Hold 1 Method to obtain the T excitation equations for the
0s of each state variable (flip flop outputs)
Digital Logic Design Page 140
Ti = (PS.external input conditions for Hold 0) + (PS.external input conditions for hold 1)
for i = 1,2,3,

Note: This method solves for the 0s of the function and it is equivalent to the first method.

Example - T Excitation-Input Equations from an ASM Chart
Obtain the excitation equations for the one-hot encoded synchronous Moore-type state machine
from the following ASM Chart.

State Y1Y2 (S0=10 and S1=01 are used and all others are unreachable)
Input X1 X2 X3
Output Z

By observing all the sets (Y1 =0 Y1
+
=1) and all clears (Y1 =1 Y1
+
=0), we can write
the T1 excitation equation, from the state diagram:

T1 = Y2.X3 + Y1.(X1.X2.X3)

Repeat the previous step for T2 using Y2 transitions
By observing all the sets (Y2 =0 Y2
+
=1) and all clears (Y2 =1 Y2
+
=0), we can write
the T2 excitation equation, from the state diagram:

T2 = Y2.X3 + Y1.(X1.X2.X3)

Note that T1 and T2 were the same. This is not the norm, and just occurred for this machine.

Based on the ASM Chart , this is a Moore machine because the output depends only on the
state variables (flip-flop output)
Z = Y2


Set Clear method for obtaining J-K Excitation-Input Equations
The following table will be used to write the JK excitation equations directly from state diagram,
ASM chart, or a timing diagram.

Z
X1.X2.X3
Z
X3
CLR
Y1
Y2
1
0
0 1
S1
S0
Digital Logic Design Page 141
Present State
(PS/NS)
Yi Yi
+


Ji Ki

Comment
User for 1s
(Set-Hold 1)
Use for 0s
(Clear-Hold 0)
0 0
0 1
1 0
1 1
0 -
1 -
- 1
- 0
Hold 0 transition
Set transition
Clear transition
Hold 1 transition

Ji
Ki

Ji


Ki
**Note: - indicates dont care

The Set Clear Method can be used to obtain the J-K excitation equations for the 1s of
each state variable (flip-lop outputs)
Ji = (PS.external input conditions for set) when Yi = 0 for i=1,2,3,
Ki = (PS.external input conditions for clear) when Yi = 1 for i=1,2,3,

Note: This method solves for 1s of the function.

We could also apply the Hold 0 - Hold 1 Method to obtain the T excitation equations for the
0s of each state variable (flip-flop outputs)
Ji = (PS.external input conditions for hold 0) when Yi = 0 for i=1,2,3,
Ki = (PS.external input conditions for hold 1) when Yi = 1 for i=1,2,3,

Note: This method solves for 0s of the function and it is equivalent to first method.

Example - J-K excitation Equation from state diagram
Design a synchronous 2-bit Binary up down counter that counts up when input signal X=0 and
counts down when input signal x=1

State Y1Y2
Input X1


Use the Set Clear Method to obtain the J-K excitation equations for the 1s of each state
variable (flip-flop outputs)
- By observing all the sets (Y1 =0 Y1
+
=1), we can write the J1 excitation equation, from
the state diagram:
J1 = Y1.Y2.X + Y1.Y2.X = Y2.X + Y2.X

- By observing all the clears (Y1 =1 Y1
+
=0), we can write the K1 excitation equation,
from the state diagram:
K1 = Y1.Y2.X + Y1.Y2.X = Y2.X + Y2.X

Repeat Step 1 for the second Flip Flop
Use the Set Clear Method to obtain the J-K excitation equations for the 1s of each state
variable (flip flop outputs)
- By observing all the sets (Y2 =0 Y2
+
=1), we can write the J2 excitation equation, from
the state diagram:
a
00
b
01
c
10
d
11
X
X
X
X
X
X
X
X
Digital Logic Design Page 142
J2 = Y1.Y2.X + Y1.Y2.X + Y1.Y2.X + Y1.Y2.X = Y1.Y2 + Y1.Y2 = Y2

- By observing all the clears (Y2 =1 Y2
+
=0), we can write the K2 excitation equation,
from the state diagram:
K2 = Y1Y2.X + Y1Y2.X + Y1.Y2.X + Y1.Y2.X = Y1.Y2 + Y1.Y2 = Y2



Digital Logic Design Page 143
5.6. FSM Design Examples
Design a 3-bit up/down binary counter.

Solution:


Step 1 State Diagram Describing the system


Step 2 - 8 possible state 3 Flip Flops required
Use D flip flop since not specified.


Step 3 Assign State variables and redraw state diagram
Zero
One
Seven Six
Note:
Counter changes with each clock which is not shown on state diagram.
up
up
up
Two
up
Down
up
Down
Three
four
down
up
down
Down
down
five
down
up
down
up
UD
0 up
1 - down

Up/Down
3-bit Binary
Counter
c
0
c
1
c
2
count 0-7
Digital Logic Design Page 144


Step 4 Excitation Input and Output Equation
Note: T= y (xor) y+


Present State Ext. Input Next State
y
2
y
1
y
0
UD D
2
=y
2
+
D
1
=y
1
+
D
0
=y
0
+

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Notes:
1) State Assignment: Binary value (y2y1y0) Equivalent to the
count.
2) Output: same as state variables (y2y1y0).
y
2
y
1
y
0

UD
000
001
111 110
0
0
0
010
0
1
0
1
011
100
1
0
1
1
1
101
1
0
1
0
Digital Logic Design Page 145


Step 5 Schematics





00
01
11
10
y
1
y
0
k
1
k
0









z
2
= y
2
+
= D
2
=
y
1
y
0
k
1
k
0









00 01 11 10
00
01
11
10
y
1
y
0
k
1
k
0





00 01 11 10
00 01 11 10
00
01
11
10
z
1
= y
1
+
= D
1
=
z
0
= y
0
+
= D
0
=
Digital Logic Design Page 146
Design a 4-botton lock (red, blue, green and black) using T flip flop. The lock will open only when
Red, Green,Black and Red buttons are pressed in sequence.


Note: Assigning 2-bit value to each button will reduce the complexity of design.

Solution:


Step 1 State Diagram Describing the system


Step 2 - 4 possible state 2 Flip Flops required
Use D flip flop since not specified.


Reset R
RGB RG
Note:
All input not shown will move the FSM to Reset State.
Red
Green
Black
Red
Key Code
k1 k0 Color
0 0 Red
0 1 Blue
1 0 Green
1 1 Black

Lock Controller
System Diagram
K0
K1
Open
0 Lock
1 - Unlock
Red Blue Green Black
Digital Logic Design Page 147
Step 3 Assign State variables and redraw state diagram


Step 4 Excitation Input and Output Equation
Note: T= y (xor) y+


Present State Input Next State Excitation Input Output
y
1
y
0
k
1
k
0
y
1
+
y
0
+
T
1
T
0
Open
0 0 0 0 0 1
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 0 1 1 0
0 1 1 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 0 0
00 01
11 10
Note:
All input not shown will move the FSM to Reset State.
00/0
01/0
11/0
00/1
State Assignment
y
1
y
0
State Name
0 0 Reset
0 1 R
1 0 RG
1 1 RGB
y
1
y
0

k
1
k
0
/Open
Digital Logic Design Page 148


Step 5 Schematics





00
01
11
10
y
1
y
0
k
1
k
0









T
0
=
y
1
y
0
k
1
k
0









00 01 11 10
T
1
=
00
01
11
10
y
1
y
0
k
1
k
0





Open =
00 01 11 10
00 01 11 10
00
01
11
10
Digital Logic Design Page 149
Design the control for a video arcade game that cost $0.50 to play. Your design should accept
quarter and nickel coins and have a return coin button.

Solution:

Step 0 System Diagram & modularization







Step 1 State Diagram Describing the system








Step 2 - possible state Flip Flops required


Step 3 Assign State variables and redraw state diagram







Step 4 Excitation Input and Output Equation







Step 5 Schematics






Digital Logic Design Page 150
Design a vending machine control that accepts nickels, quarters and dollar bills. All products are
priced at $1.00. User may select one of 25 products that will be delivered once user has deposited
sufficient funds..
Note: Use modularization to breakdown the design to modules to reduce the design complexity of
each design.

Solution:

Step 0 System Diagram & modularization







Step 1 State Diagram Describing the system








Step 2 - possible state Flip Flops required


Step 3 Assign State variables and redraw state diagram







Step 4 Excitation Input and Output Equation







Step 5 Schematics







Digital Logic Design Page 151
5.7. Additional Resources
Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 8 Sequential Logic Design Practices
Digital Logic Design Page 152
5.8. Problems
Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.
Digital Logic Design Page 153
Chapter 6. Finite State Machine Optimization & Testing

6.1. Key concepts and Overview
State Minimization and FSM Design Process
State Minimization/Reduction Using Implication Chart (or Table)
Design for Testability (Scan test, Linear Feedback Shift Register and primitive Polynomials)
Additional Resources
Problems
Digital Logic Design Page 154
6.2. State Minimization and FSM Design Process
The state minimization is done after the fourth step of the seven steps of Finite State Machine (FSM)
classical design:

1) Organize the Design Specifications Using one or more of the following:
Timing Diagram, State Diagram, ASM Chart or Present State/Next State (PS/NS) table

2) Determine the number of flip-flops based on the number of states.
Full encoding 2
#flip-flop
# states
or
one-hot encoding #flip-flop = # States

Next assign one present state variable to each flip-flop output.

3) Assign a unique code to each state (a specific value for present-state variables).

4) Select the flip-flop type to be used, then determine the excitation input equations and the Moore
and/or Mealy output equations.

The excitation-input equations for common flip-flops are shown below:
JK Y
+
= J.Y + K.Y
T Y
+
= T
XOR
Y
.D Y
+
= D


5) Draw the circuit schematic (pencil/paper or CAD tools).

6) Perform a simulation to test the functionally of the design.

7) Implement the design in hardware.

State Minimization using
implication Chart is used
at this point
Digital Logic Design Page 155
6.3. State Minimization Using an Implication Chart (or Table)
The Implication Chart Method is a systematic approach to find the states that can be combined into a
single reduced state. This method is cumbersome to do by pencil and paper, but it is well-suited for
automation because it is a systematic approach.

Minimization procedure with an Implication Chart
A 3-bit sequence detector example is used here to demonstrate the Implication Chart use in state
minimization.

Problem Statement
Design a binary sequence detector with the minimum number of states that outputs a 1
whenever the machine has observed the serial input sequence 010 or 110.

Step 1) Use the problem statement to write the Present/Next State Table
(It may help to first do a state diagram.)


Input Sequence

Present State
Next State
X=0 X=1
Output
X=0 X=1
Reset S
0
S
1
S
2
0 0
0
1
S
1

S
2

S
3
S
4
S
5
S
6

0 0
0 0
00
01
10
11
S
3

S
4

S
5

S
6

S
3
S
4
S
5
S
6
S
3
S
4
S
5
S
6

0 0
1 0
0 0
1 0

Step 2) Draw an implication Chart which allows entries relating every state with every other
state as shown below:
- Label vertically from last state (S6) to second state (S1)
- Label horizontally from first state (S0) to next to the last state (S6)

Digital Logic Design Page 156

In general for an n-state machine, we will have (n
2
- n)/2 cells. Each of the cells in the
implication chart relates State Sj with State Si.

Note: The order is not important.

Step 3) Fill-in each cell (Xij) in the implication table with one of the following two options:
- X if the Si and Sj have different outputs.
(state output for Moore machine and transition output for the Mealy machine)
- Transition states for Sj and Si for each of the inputs
This means that the next states for all possible inputs must be equivalent for these states
to be equivalent.







S
1

S
2

S
3

S
4

S
5

S
6















S
0
S
1
S
2
S
3
S
4
S
5

Digital Logic Design Page 157
After the application of previous two rules we will end up with the following table.
Note: At this stage, many of the states have been eliminated.

Step 4)
We go through the chart repeatedly until a complete pass can be done through the chart
without making any additional X markings.

- First Marking Pass we are looking for cases where the dependencies are not valid.

For example, for States S0 and S1 to be equivalent, we must have S1 S3 equivalent
and S2 S4 equivalent.

Since the cells relating S2 and S4 are crossed out, then the S0 and S1 cell must be
crossed out. Continue this process (top-down and left to right) through the chart.
S
1
S
3

S
2
S
4

S
1
S
5

S
2
S
6

S
1
S
3

S
2
S
4


X
S
1
S
3

S
2
S
4

X
S
1

S
2

S
3

S
4

S
5

S
6

S
3
S
5

S
4
S
6

S
3
S
3

S
4
S
4


X
S
3
S
3

S
4
S
4

X
S
5
S
3

S
6
S
4

X
S
5
S
3

S
6
S
4

X
X
S
3
S
3

S
4
S
4

X
X
S
5
S
5

S
6
S
6

X
S
0
S
1
S
2
S
3
S
4
S
5

Mean S0 S1 and S1 S3 when X=0.
Mean S0 S2 and S1 S4 when X=1.
Digital Logic Design Page 158


- Second marking pass.
Repeat the process with the resulting chart from the previous pass.

In this pass, no change was made to the table so this is the last pass. The table
X
X
S
1

S
2

S
3

S
4

S
5

S
6

S
3
S
5

S
4
S
6

X
X
X
X
X
S
3
S
3

S
4
S
4

X
X
X
S
0
S
1
S
2
S
3
S
4
S
5

X
S
3
S
3

S
4
S
4


S
5
S
3

S
6
S
4

X
S
3
S
3

S
4
S
4


S
5
S
3

S
6
S
4

X
X
S
5
S
5

S
6
S
6

S
3
S
3

S
4
S
4


S
1
S
3

S
2
S
4

S
1
S
5

S
2
S
6

S
1
S
3

S
2
S
4


X
S
1
S
3

S
2
S
4

X
S
1

S
2

S
3

S
4

S
5

S
6

S
3
S
5

S
4
S
6

X
S
3
S
3

S
4
S
4

X
S
5
S
3

S
6
S
4

X
S
5
S
3

S
6
S
4

X
X
S
3
S
3

S
4
S
4

X
X
S
5
S
5

S
6
S
6

X
S
0
S
1
S
2
S
3
S
4
S
5

Digital Logic Design Page 159
indicates that the following states are equivalent:

S
0
does not have equivalent, so it will need a new designator Y
0
state
S
1
S
2
S
3
S
5
are equivalent so they can be called Y
1
state
S
4
S
6
are equivalent so they both can be called Y
2
state

Step 5) Present/Next State Table for the minimized state machine:


Input Sequence

Present State
Next State
X=0 X=1
Output
X=0 X=1
Reset Y
0
Y
1
Y
1
0 0
00,01 or 10 Y
1
Y
1
Y
2
0 0
01 or 11 Y
2
Y
1

Y
2
1 0

Digital Logic Design Page 160
6.4. Design for Testability (DFT)
During the design phase, you need to consider the testing needs. Here are a few key types of testing to
consider:

Go/No Go Testing
The goal of this test is to ensure that the product is functional before delivering it to the customer.
This type of test indicates whether the product is functional and can be shipped or not.

Diagnostic Test
As the name implies, this test is typically used to find which subsystem is failing, so it can be replaced
or repaired. This type of test benefits from testability consideration during the design phase.

With the proper attention to Design For Testability (DFT), the diagnostic test will:

1) Be easier to develop.
2) Be more effective in finding problems earlier.
3) Reduce downtime, and may even test while the system is operating, which leads to failure
prediction.
4) Reduce cost of a failed product in production phase as well as within warranty.

Testing
Digital designs are tested by applying test vectors, which are a set of input values and expected
output values.

Simplification Assumptions
In the worst case scenario, we require 2
n
vectors to test an n-input combinational circuit. So,
engineers make assumptions about the type of errors in order to simplify the process:

Single bit fault
Here the assumption is that only one bit (or line or pin) may be stuck at 1 or 0 incorrectly.

Using an 8-input AND gate to demonstrate the benefit of this simplification, instead of
needing 2
8
or 256 vectors, we can fully test this circuit with the following nine vectors (walking
the 0):

[11111111] [01111111] [10111111] . . . [11111011] [11111101] [11111110]

Test-generation programs
When the system is more complex, it is hard to impossible to create test vectors by hand.
There are programs designed to create test vectors based on circuit design to ensure that the
product functions so that all design requirements (customer needs) are met.

DFT methods attempt to simplify test-pattern generation by enhancing the controllability and
observeability of logic elements in the circuit.

- In a circuit with good controllability, it is easy to produce any desired values on the
internal signals of the circuit by applying an appropriate test-vector input combination to
the primary input. You may even add additional inputs just for testing.

- In a circuit with good observeability, any internal signal value can be easily propagated to
a primary output for comparison with the expected output. You may even add additional
outputs just for testing.

Digital Logic Design Page 161
Bed-of-Nails and In-Circuit Testing
In a digital circuit that is on a PC board (PCB), most manufacturers use a cushion of probes
(nails) that makes contact with every signal in the PCB. Then it can be used to drive through the
control points and observe the results at observation points.

Although these devices are expensive, they allow the manufacturer to test a circuit in seconds
and have the confidence that all critical circuits operate to the specification.

Agilent and Tektronix are two of the largest in-circuit test solution vendors.

Scan Method
An in-circuit test cannot test custom ICs and FPGAs, since internal signals are not accessible.
Even with many PCBs, the high-density and surface mounting have limited their effectiveness.

A scan method attempts to control and observe the internal signals of a circuit using only a small
number of test points.

A scan-path method considers any digital circuit to be a collection of flip-flops or other storage
elements interconnected by combinational logic.

The basic idea of a scan test is to control and observe the state of storage elements. It does this
by providing a normal operation mode and a separate scan operation mode where the storage
elements are reorganized into a giant shift register (Linear Feedback Shift Register) to test the
storage elements

Here is a sample:
Note: Heavier dashed lines indicate the Scan Path

Note: For a more robust scan test, input pattern are designed using Primitive polynomials. Each
polynomial offers a different level of coverage and error detection. This area represents an opportunity for
Comb.
Logic
.


Primary
Input
D Q
T
TE
CLK
D Q
T
TE
CLK
Comb.
Logic
Clock
EN_SCAN
SCAN IN
D Q
T
TE
CLK
D Q
T
TE
CLK
Comb.
Logic
Primary
Output
.


SCAN OUT
Digital Logic Design Page 162
further research by the reader.

Digital Logic Design Page 163
6.5. Additional Resources

TBC
Digital Logic Design Page 164
6.6. Problems
Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.


Digital Logic Design Page 165
Chapter 7 Verilog . Verilog Hardware Description Language (Verilog)

7.1. Key concepts and Overview

History
Introduction to Verilog VHDL
Syntax
Assignments
Operators
Variable Types and Declarations
Flow Control Statements
Code Modularization
Additional Resources
Problems
Digital Logic Design Page 166
7.2. History

Hardware Description Language (HDL) is used by designers to describe circuit functionality in high level
language. HDL design is then processed to implementable hardware circuit design.

The two main HDL development solutions on the market are Verilog Hardware Design Language
(Verilog) and Very high-speed integrated circuit Hardware Design Language (VHDL). Although Verilog
came on the market much earlier than VHDL, they both have equal market share currently.

Verilog
Introduced by Gateway Automation in 1984 as a proprietary language.
Purchases by Synopsis in 1988 which was eventually purchased by Cadence Design Systems.
Cadence Design System has successfully has successfully market Verilog to a market power
house.
Verilog was standardized as IEEE 1364 in 1995.
The syntax is similar to C language.

VHDL
The US department of Defense (DOD) and the IEEE sponsored the development of VHDL
Standardized by IEEE in 1993.
Design may be decomposed hierarchically.
Each design element has a well-defined interface and a precise behavioral specification.
Behavioral specification can use either an algorithm or by a hardware structure.
Concurrency, timing, and clocking can all be modeled (asynchronous & synchronous
sequential circuit).
The syntax is a mix of Pascal and Ada software languages.

This chapter focuses exclusively on Verilog Hardware Description Language commonly refered to as
Verilog. There are sufficient similarity in structure and concepts between VHDL and Verilog that learning
one will significantly reduces the time required to learn the second language.

This chapter does not attempt to describe the complete Verilog HDL rather it introduce key concepts
underlying Verilog HDL and basic programming tools. Most Verilog development environment provide an
extensive reference which should be utilized in conjunction with this material.
Digital Logic Design Page 167
7.3. Introduction to Verilog HDL
The process of design is shared amongst the Hardware Description Languages (Verilog & VHDL) and
may be divided into front-end and backend as outlined below:

The Front-end section is where all the decision are made and the design is documented.
The Back-end section includes the implementation, and testing the product.

Although this process is iterative by its very nature, as the distance between the step that an error is
discovered and the step that the correction is made increases, the cost (time & resource) increases
exponentially.

Design can use only one or a combination of the following approaches (levels of abstraction) to describe
the design:

Gate or Switch level
Design by describing the circuit in term of gates such as and, or, etc.
Register-Transfer Level (RTL)
RTL describes the circuit using operations and the transfer of data between registers.
Behavioral Level
At this level of abstraction, the circuit is described in a number of concurrent algorithms
describing the circuit behavior. This level of design is less hardware implementation specific.

Module is the basic block in Verilog. Before getting to language syntax and specifics, here is a example
code for a positive edge (rising edge) D Flip Flop. This is considered Behavioral-level design since we
are describing the behavior instead of specific gates (gate-level) or how the data flows amongst the
registers (RTL).

As always, start with a system diagram|

Example Verilog
Design a positive edge triggered D-FF using Verilog/
hierarchy/
block diagram
(Step 1)
coding

(Step 2)
compilation

(Step 3)
simulation/
verification
(Step 4)
timing
verification
(Step 7)
fiting/Place+
route
(Step 6)
Synthesis

(Step 5)
Design
Requirements
Back-end
Steps
Front-end
Steps
Digital Logic Design Page 168
SOLUTION:

Now, the Verilog code that describes the D flip flop design:



`timescale 1ns/100ps // time measurement unit is 1 nsec with 100 ps percision

// Design a D flip flop
// Author: Instructor
// Last Update: 6/5/2013

module D_ff(clock, d, q); // defines the input and output into module

input clock, d; // define input
wire clock, d; // declare input type

output q; // define output
reg q; // declare output

// Body of the design
always @ (posedge clock) // executes following code at every clock rising edge
begin
q <= d; // make an assignment
end

D
Flip Flop
Q
D
CLK
Digital Logic Design Page 169
7.4. Syntax
Verilog HDL Syntax is similar to C programming Language. Below are some of the Verilog basic
language syntax:

Identifiers
Variables, labels and module names are identifier. Verilog allows identifier to be specified by letters
or underscore followed by more letters, digits, dolor sign ($) or underscore (_) up to a maximum of
1024 character. Below are few examples of valid identifiers:
test_213?
count
_count

Note that Reserve words (Verilog commands and keywords) may not be used as identifiers:

always
and
assign
attribute
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
ifnone
initial
inout
input
integer
join
medium
module
large
macromodule
nand
negedge
nmos
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
signed
small
specify
specparam
strength
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
unsigned
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor

Comment
Any information appearing after // on a line is considered comment:

// this is comment for the reader

Like C, Verilog considers text between /* and */ as comment and it may span multiple lines

/* firs line of comment
could more line
then end here */

Case Sensitivity
Verilog is case sensitive which means keywords and variable must be in correct case or it will not be
consider the same. For example Count and count are two variables. By the way all keywords in
Verilog are in lower case. In this document all keywords are in bold.

Digital Logic Design Page 170
Number Representation
Number may be represented in decimal form with or without sign (+12 or -24). Additionally, Verilog
allows for a more precise description by using the following format for defining a number:

<sign><size><base><number> where
<sign> can be + or -; if not specified, it is positive
<size> is the number of bits (in decimal)
<base> is the number base which is a letter
b is binary
o is Octal
d is decimal
h is hexadecimal
<number> is the number using digits available in specified base)

Below are a few examples of specifying numbers:

294 // default type is decimal
h2FA // hex number but size is not specified
5b11 // 5 bit binary number 00011
+4b1011 // 4 bit positive binary number 1011
-3b101 // 3 bit negative binary number 101
5b1110x // 5 bit positive binary number with do not care least significant bit
hff // default 16 bit number 00ff hex
16hff // explicitly defined 16 bit number 00ff hex
1b1 // 1 binary
1b0 // 0 binary
1bx // x binary or one unknown bit
1bz // one hi-z bit
32H0ZX1FABX // hexadecimal 32 bits representing binary
// 0000 zzzz xxxx 0001 1111 1010 1011 xxxx
8b0110_1100 // 8-bit binary 01101100
4b1x0z // four bits 1X0Z
18o7573 // 18 bits octol or 000 000 111 101 111 011 binary
7d 126 // 7 bits decimal 123 or 01111010

String Representation
A string is a sequence of character enclosed in double quotes. for examples This is an Example.

Logic Values
Verilog utilizes four logic values:

0 // false, low, zero
1 // true, high, one
z or Z // High Impendance or floating for use with tri-state devices
x or X // Uninitialized or unknown value

Verilog also allow for logic strength definition which is useful for situations where multiple devices are
driving the same wire in determining the logic present on the wire.

Module Definition
As discussed earlier module is the basic block of Verilog and is similar in nature to function in C with
added attributes for describing circuit design.

module yourModuleName(inPort1,,outPortb1,); // start of module with input and output
// identifiers

Digital Logic Design Page 171
// system definition in terms of external port (input and output)
input inPort1, ; // Ports inPort1, are set as inputs
wire inPort1, ; // inPort1, are declared as wires
output outPort1, ; // Ports outPort1, are set as outputs
reg outPort1, ; // a and b are the two button inputs

// The code that performs the logic of this module goes here
statements // Module Body

endmodule // end of module

Digital Logic Design Page 172
7.5. Assignments
Verilog understand that there two types of element in digital design:

Combinational gates and other circuitry with no memory
Sequential flip flop and other circuitry with memory

In order to handle both types of element, Verilog identifies three types of blocks to direct the execution of
a module functionality. The three blocks are initial, assign and always which are described in detail
below:

Initial Block initial
Initial statement ensures that the assignments are made only once at the beginning during the
simulation. It is typically used to initialize variables at the start of the code. Below is a usage
example:

Assign Block assign
Assign statement is used for modeling only combinational logic and it is executed continuously.
So assign statement called continuous assignment statement as there is no sensitive list.

for example in the following statement, value of variable present will be set to value in next as
long as the code is active.

assign present=next;

Note assign does one statement at a time and sequentially and it is used for combinational login
only.
module example(Ain, Bin, Cout);

input Ain, Bin;
wire Ain, Bin;
output Cout;
wire Cout;
Integer i, count;

Initial // set the initial value of variables.
Begin
i = 0;
count =0;
Ain =0;
Bin =0;
end //initial

endmodule // end of module


Digital Logic Design Page 173
Below is usage example in a module:

Always statement always
Always block not only executes always (on going) as the name implies but it also allows for
selective execution based on the sensitivity list.

In the following example input Ain is always assigned to Cout. As you can see this is similar
function to assign with the difference that we have to specify a delay. In the following example
we are using a delay of 5 time unit (time unit are defined at the beginning of code). The value of
delay is written after the # symbol.
`t i mescal e 1ns/ 100ps / / t i me uni t i s 1 ns wi t h pr eci si on of 100 ps

module example(Ain, Bin, Cout);

input Ain, Bin;
wire Ain, Bin;
output Cout;
reg Cout;
Integer i, count;

Initial // set the initial value of variables.
Begin
i = 0;
count =0;
Ain =0;
Bin =0;
end //initial

assign Cout = Ain; // Cout is always equal to Ain
assign #5 Cout=Bin; // 5 unit delay (5 ns) before assignment

endmodule // end of module


Digital Logic Design Page 174

If modify the above code by adding a sensitivity list which includes Bin and a clk. now the always
block will only be executed when Bin or clk change.
It is important to remember that always block cannot make an assignment to a wire but can drive
reg and integer data typed.

If we go back to the d-ff example, you see that always can be triggered on specific type of
module example(Ain, Bin, clk, Cout);

input Ain, Bin, clk;
wire Ain, Bin, clk;
output Cout;
reg Cout;
Integer i, count;

Initial // set the initial value of variables.
Begin
i = 0;
count =0;
Ain =0;
Bin =0;
end //initial

always @ (Bin, clk) //Executes only when clk or bin change
begin
Cout = Ain; // Cout is equal to Ain only if clk or Bin have changed.
end
endmodule // end of module
module example(Ain, Bin, Cout);

input Ain, Bin;
wire Ain, Bin;
output Cout;
reg Cout;
Integer i, count;

Initial // set the initial value of variables.
Begin
i = 0;
count =0;
Ain =0;
Bin =0;
end //initial

always
begin
# 5 Cout = Ain; // Cout becomes equal to Ain after delay of 5 time unit
end
endmodule // end of module
Digital Logic Design Page 175
change. in the following example the assignment is only triggered when the positive edge of clk is
encountered.
As you can see the assignment for q in the D flip flop example uses <= and not =. These two
assignment operators have distinct functionality:

= is a blocking assignment and is used for combinational logic assignment. This operator
allows parallel assignment so anytime the expression changes, the output will change also.

"<=" is a non-blocking assignment operator and is used for sequential logic. <= assignment
operator results in sequential execution (blocks concurrent execution) in always block.

`timescale 1ns/100ps // time unit is 1 ns with precision of 100 ps

// Design a D flip flop
// Author: Instructor
// Last Update: 6/5/2013

module D_ff(clock, d, q); // defines the input and output into module

input clock, d; // define input
wire clock, d; // declare input type

output q; // define output
reg q; // declare output

// Body of the design
always @ (posedge clock) // executes following code at every clock rising edge
begin
q <= d; // make an assignment
end

endmodule // end of module note there is no ;
Digital Logic Design Page 176
7.6. Operators
This section provides an overview of logical, relational, arithmetic and other operators. Note that this a
sampling of operation available and the reader is encouraged to explore Verilog reference manual online.

Logical operators
The logical operators and, or and not as list here. They operate on two variables regardless if the
variables are one bit, scalar or array of bits.

Symbol Operation
! Negation
&& And
|| Or

The following function are bitwise operators and the operands must be one bit or array of bits.

Symbol Operation
& And
~ Negation
~& Nand
| Or
~| Nor
^ Xor
~^ Xnor
>> Right shift
<< Left shift

Example - TBA



Relational operators
Relational operators are used to test the relative values of two scalar types. The result of a relational
operation is always a Boolean true (1) or false (0) value.

Symbol Operation
== Equality
!= Inequality
> Greater than
< Less than
>= Greater than or equal
<= Less than or equal

Example - TBA


Arithmetic Operations
The Arithmetic operators are listed in this section

Symbol Operation
* Multiply
/ Divid
+ Add
- Subtract
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% Modulus

Example - TBA


Others
Here are a couple of useful ones:

Concatenation {}
Attaches two strings or bit arrays together. for example {A,B}

Example - TBA

Conditional ?
Allows making assignments based on a condition.

Example -

x=(enable)?A:B; //x=A if enable is true otherwise x=B

Example Need to add examples to each section.
a = b + c ; // simply adds b and c and saves it in a
a = 1 << 3; // '1' left by 3 position.
a = ~b ; // inverts every bit in b and saves it in a.
a = !b ; // If b is true (non zero) then a will be false
Digital Logic Design Page 178
7.7. Types and Variable Declarations
Verilog requires explicit declaration of variables which means before using a variable it must be declared.
It is important to note that Verilog performs automatic type conversion. Variables in general are either of
the net data type or variable data types.


Net Data Types
wire is a Net data type which means it must be driven. Typically input port is of the type wire. Net
data type is used to connect components and can have strength modifiers supply0, supply1, strong0,
strong1, pull0, pull1, weak0, weak1, highz0, highz1, small, medium, large). Wire is implements
interconnection.

Example -
wire clk; // clk is declared as wire which need to be driven

Variable Data
A Variable data type behaves similar to variables in c, it changes its value upon assignment and
holds its value until another assignment. The five common Variable types are:

integer Type
integer is typically a 32 bit 2s complement integer.

Example -
integer count; // declare count as an integer

real
Type real is typically a 64 bit using the double precision floating point IEEE Standard format.

Example -
real earnedSalary;

realtime
realtime is used to storing time as a real type (floating point value).

Example -
realtime now;

reg type
By default reg is a one bit unsigned value and may have a sign modifier. It could use a vector
modifier [msb:lsb] to declare a multi-bit reg. We typically use reg to declare the output port type
and is typically implemented using flip flops.

Example -
reg done; // declare done as a one bit value
reg [15:0] results; // declare results as a bit vector with bits 0 as least significant bit (lsb)
// and 15 as the most significant bit (msb)


time type
The system function $time returns simulation time in time type. In most systems time is 64 bit
unsigned integer value.

Digital Logic Design Page 179
Example -
time thisTime; // declare thisTime to store time


Any of the types may be groups as arrays by adding by adding modifier [first:last]. you may use index to
refer to each of the array members. Remember, Verilog does not allow access to a range of array
members. In other word list[2:5] is a n illegal operation. Below are example of arrays:

integer [1:20] grades; // integer type array with 21 element with first element at grades[1]
// and the last element at grades[20]

real [0:30][0:90] gisCord; // You can even make a multi-dimension array by
// adding modifier [first][last] for each dimension.

Vectors is array of multiple bit types by adding modifier [msb:lbs]. For example:

wire [15:0] exTest; // wire type with 16 bit with lsb at exTest[0] and msb at exTest[15]

wire [-5:5] exTest; // wire type with 11 bit with msb at exTest[-5] and lsb at exTest[5]

reg [13:-2] results; // reg type with 16 bits with lsb at results [-2] and msb at [13]

reg signed [31:0] results; // reg type with 32 bits in 2s complement.


Digital Logic Design Page 180
7.8. Flow Control Statements
Verilog much like C programming languages provides a wide variety of flow control statement. This
section will cover some of the most common flow control statements including if-else, case, for, and
while. Even though the functionality and syntax are similar C programming language

Even though the functionality appears to be the same as C, Verilog is an Hardware description language
so the codes has to translate to hardware. Meaning, that from time-to-time, special care needs to be
taken to ensure that design is implementation in hardware.

If-else Statement
if-else statement will execute the T statements if the conditions are true and execute the F
statements otherwise. The syntax is shown below:

Example -


Case Statement
Case statement is preferred approach instead of complex nested if-else statements. Case statements
allows selection of a specific set of statements to be executed based on the specific values of a
selection variable.

Example -

case (caseExp) // Select Variable
exp1 : statements 1 ; // if caseExp = exp1 then statement1 will be executed
exp2 : statements 2; // if caseExp = exp2 then statement2 will be executed
exp3 : statements 3; // if caseExp = exp3 then statement3 will be executed
default : statements; // if none of value matched then this statement is executed
endcase
// simple if-else statement
if (test == 1b1)
begin
count = 2;
wr_data = 16hAE;
end
else
begin
count = count - 1;
wr_data = 0;
end
if (condition) // condition is a logincal operation resulting in true or false
begin
T Statements // if condition is true, execute T Statements
end
else
begin
F Statements // if condition is true, execute F Statements
end
Digital Logic Design Page 181
case(step)
0 : $display ( "starting step );
1 : $display ( "step number 2" );
2 : $display ( "step 3" );
default : $display ( "undefined step" );
endcase

While Loop
statements in while loop executes a code segment as long as the while condition is true. While loop
syntax is shown below:

Example -

count = 0;
while (count < 12)
count = count +3;
end

For Loop

Example -

// This code displays counts from 0 to 30.
for (count= 0; count < 31; count = count +1) begin
$display ( "Count is %d" , count);
end


for (initial; condition; end expression) // first initial will be done, if the condtion is true then
// for loop body is executed and at the end of loop
// execute the end expression.
begin
// for loop body
Statements
end
While (condition) // while condition is true the statements is executed and
// when condition is false, the loop will be terminating.
begin
Statements
end

Digital Logic Design Page 182
7.9. Code Modularization
As the code gets more complex and size increases, it is important to modularize the code by developing
the code as multiple modules. This approach improves code reusability, improved debugging/reliability
and simpler design.

Here is example of how multiple modules are used:


// Modularized code
// First write the module you plan to use latter
module mod_base(inA,inB,outA);
input inA,inB;
wire inA, inB
output outA;
reg outA;
assign outA=(inA)?inB:1b0;
endmodule

// now write the main circuit that uses our selector
module main(a,b);
input a,;
wire a;
output b;
reg b;
// now used mod_base
mod_base U1(1b0,1b1, temp); // this is where the mod-base is instantiated and used.
endmodule

Digital Logic Design Page 183
7.10. Additional Resources

Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 5 Hardware Description Language

Palnitkar, S. Verilog HDL (2012) Prentice Hall

Digital Logic Design Page 184
7.11. Problems

Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.


Digital Logic Design Page 185
Chapter 8 VHDL . VHDL Hardware Description Language (VHDL)

8.1. Key concepts and Overview

History
Steps in HDL design
Architecture and Program Structure
Declarations
Operators
Structural Design Elements
Behavioral Design Elements
Dataflow Design Elements
Additional Resources
Problems
Digital Logic Design Page 186
8.2. History

Hardware Description Language (HDL) is used by designers to describe circuit functionality in high level
language. This VHDL design is then processed to an implementable hardware circuit design.

The two main HDL solutions on the market are Verilog Hardware Design Language (Verilog) and Very
high-speed integrated circuit Hardware Design Language (VHDL). Although Verilog came on the market
much earlier than VHDL, they both have equal market share currently.

Verilog
Introduced by Gateway Automation in 1984 as a proprietary language.
Purchases by Synopsis in 1988 which was eventually purchased by Cadence Design Systems.
Cadence Design System has successfully has successfully market Verilog to a market power
house.
The syntax is similar to C language.

VHDL
The US department of Defense (DOD) and the IEEE sponsored the development of VHDL
Standardized by IEEE in 1993.
Design may be decomposed hierarchically.
Each design element has a well-defined interface and a precise behavioral specification.
Behavioral specification can use either an algorithm or by a hardware structure.
Concurrency, timing, and clocking can all be modeled (asynchronous & synchronous
sequential circuit).

This chapter focuses on VHDL exclusively. There are sufficient similarity in structure and concepts
between VHDL and Verilog that learning Verilog is expected to be a simple process.
Digital Logic Design Page 187
8.3. Steps in VHDL design
The process of design may be divided into front-end and backend. Where:
The Front-end section includes all the decision are made and the design is documented.
The Back-end section includes the implementation and testing and the product.
Although this process is iterative by its nature, as the distance between the step that an error is
discovered and the step that the correction is made increases, the cost (time & resource) increases
exponentially.


Program Structure

VHDL was designed with principles of structured programming in mind and borrowed ideas from
Pascal and Ada Software Languages.

VHDL Code has two parts (entity & architecture)
Entity
A declaration of a modules inputs and outputs. Entity is viewed as a wrapper for the
architecture, hiding whats inside, while providing access for another module to use the
functionality.

Architecture
A detailed description of the modules internal structure or behavior.



VHDL is hierarchical, meaning that a higher-level entity may use other entities while hiding lower
level entities from the higher level ones as shown by the following diagram:
Entity Declaration
Architecture
Definition
-- Eight-bit comparator
entity ent_compare is
port( A, B: in bit_vector(0 to 7);
EQ: out bit);
end ent_compare;

architecture arc_compare of ent_compare is
begin
EQ <= 1 when (A = B) else 0;
end arc_compare1;
hierarchy/
block diagram
(Step 1)
coding

(Step 2)
compilation

(Step 3)
simulation/
verification
(Step 4)
timing
verification
(Step 7)
fiting/Place+
route
(Step 6)
Synthesis

(Step 5)
Design
Requirements
Back-end
Steps
Front-end
Steps
Digital Logic Design Page 188

General VHDL Semantics
VHDL similar to other languages has many constructs and rules. The following list contain some of
the most common Semantics:

Code can span multiple lines and files for larger designs.

Comment field starts with --" and ends at the end of line.

Each statement must be terminated with a ;.

VHDL ignores space and line breaks which allows for readability formatting.

VHDL has many reserved words (or keywords) that cannot be redefined such as:
Entity, Port, Is, In, Out, End, Architecture, Begin, When, Else, Not, ...

Reserve words and identifiers are not case-sensitive

User Defined Identifiers
These are names used to refer to variables, signals, types, processes, function, types,
architecture and entities. User defined identifiers names must adhere to the following
requirements:

Must begin with a letter and contain letters, digits and underscores.
Underscore cannot follow each other and cannot be the first or last character.
Reserve words are not allowed.

Architecture A
Entity A
Architecture B
Entity B
Architecture C
Entity C
Architecture D
Entity D
Architecture E
Entity E
Architecture F
Entity F
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8.4. Entity and Architecture
The remainder of this document discusses the VHDL infrastructure, common structures and syntax. The
reader is encouraged to use the VHDL development tools such as Active-HDL from Aldec to implement
the ideas discussed in this text. Additionally, the reader is encouraged to use the online documentation
and help section of these products to explore related capabilities of VHDL.

This section focuses on the core framework of VHDL (Entity and Architecture).

Entity Declaration
Entity code describes the system diagram which includes definition of input and output. It does not
provide any information on the internal function of the device.

entity entity_name is
port (
signal_names : mode signal_type;
signal_names : mode signal_type;
. . .
signal_names : mode signal_type);
end entity_name;

entity_name
A user defined identifier to name the entity.

signal_names
A comma-separated list of one or more user-selected identifiers to name external-interface
signals.

mode
Signal_type for mode may be set to one of the following four reserved words in order to
specifying the signal direction:

- in
The signal is an input to the entity.
- out
The signal is an output of the entity. Note that the value of such a signal cannot be read
inside the entitys architecture, only by other entities that use it.
- buffer
The signal is an output of the entity, and its value can be also be read inside the entity
architecture.
- Inout
The signal can be used as an input or an output of the entity. This mode is typically used
for three-state input/output pins on PLDs.

Signal-type
A built-in or user-defined signal type. Discussed later. Note there is no ; after the last signal-
type.


Digital Logic Design Page 190
Architecture Definition
Architecture code defines the function of the device. It is highly recommend that pseudo code or
other high level design be completed prior to writing the architecture code.

architecture architecture_name of entity_name is
signal declarations;
type declarations;
constant declarations;
function declarations;
procedure declarations;
component declarations;
begin
concurrent_statement;
. . .
concurrent_statement;
end architecture_name;

architecture_name is a user-defined identifier, and entity_name is also a user defined identifier
for the entity. The concurrent-statements can appear in any order since they are executed
currently. The Declaration statement may also appear in any orders..

Digital Logic Design Page 191
8.5. Declarations
Signal and Variable Declarations
Signal declaration gives the same information about a signal as in a port declaration, except that
mode specification is not required. Syntax for signal declaration is shown below:

signal signal_names : signal_type;

Any number of signals can be defined within architecture, and they roughly correspond to the named
wires in a logic diagram.

It is important to note that symbol <= is used to assign a value to a signal. For example to assign a
value of 4 to a signal stemp, it needs to be written as follows:
stemp <= 4;


VHDL variables are similar to signals except that they do not have a physical significance in a circuit.
Variables are used within functions, procedures and processes (not used in architecture definition).
The variable declaration syntax is as follows:

variable variable_name : variable_type;

It is important to note that symbol := is used to assign a value to a variable. For example to assign
a value of 4 to a variable vtemp, it need to be written as follows:
vtemp := 4;

type Declarations
All signals, variables and constants in a VHDL program must have an associated type. Each type
specifies the range of values that object can take on. type may be pre-defined or user defined.

Pre-Defined Types:

Bit
Takes on 0 and 1 values
Bit-vector
array of bits
Boolean
True, False { EQ <= True;}
Integer
A whole number ranging from -2
31
+1 through +2
31
-1 {count <= count + 2;}
Real
1.0, -1.0E5 {V1 := V2 / 5.3}
Character
All of the ISO 8-bit character set the first 128 are the ASCII Characters. {CharData <= X;}
Note: The symbol is used for character definition.
String
An array of characters {msg<=MEM: & Addr;}
Note: The symbol is used for string definition.
Time
1 us, 7 ns, 100 ps {Q<=1 after 6 ns;}


Digital Logic Design Page 192
Predefined Operators
VHDL is a strongly typed language which means that the complier issues error messages if types
in an operation or assignment do not perfectly match.

The integer and Boolean Operations are the most commonly used VHDL operation and operands
in each operation group must have the correct type in order for the operation to be compiled
correctly.

Following table list some of the most common operations:

Integer Operators Boolean Operators
+
-
*
/
mod
rem
abs
**
addition
subtraction
multiplication
division
module division
module remainder
absolute value
exponentiation
and
or
nand
nor
xor
xnor
not
AND
OR
NAND
NOR
Exclusive OR
Exclusive NOR
Complementation

User-Defined Types
Although VHDL provides an extensive list of pre-defined types, user may need to define new
types using the user-defined type capabilities of VHDL. The flowing pages, describe the most
common user-defined type constructs:

Numeration
Numeration enables the user to define a type that can only accept a predefined set of values.
The following syntax, allow definition of numeration type and its use to build two different type
of arrays:

type type_name is (value_list); -- Value-list is a comma-separated list of all
-- possible values of the type

-- create an array of type-name with an ascending order from start to end
subtype subtype_name is type_name range start to end;

-- create an array of type-name with a descending order from start to end
subtype subtype_name is type_name range start downto end;

- Example Write a code segment to define an array that starts from 20 to -4 with each
element value restricted to either red, green, or blue.

type COLORS is (red, -- User-define types are typically in Capital Letters
green,
blue,
);
subtype my_colors is COLORS range 20 downto -4;

- Example- Define a complete logic type that includes hi-z, weak and forcing.

type STD_ULOGIC is (
U, -- Uninitialized
X, -- Forcing Unknown
0, -- Forcing 0
1, -- Forcing 1
Z, -- High Impedance
Digital Logic Design Page 193
W, -- Weak Unknown
L, -- Weak 0
H, -- Weak 1
-, -- Dont care
);
subtype STD_LOGIC is resolved STD_ULOGIC


Array
The following list represent the most common use of array constructs:

type type_name is array (start to end) of element_type;
type type_name is array (start downto end) of element_type;
type type_name is array (range_type) of element_type;
type type_name is array (range_type range start to end) of element_type;
type type_name is array (range_type range start downto end) of element_type;

- Inside the VHDL program statement array element can be accessed using array name of
indices. Note that the leftmost element is the first.

Examples:
type monthly_count is array (1 to 12) of integer; -- 12 element array m(5)
type byte is array (7 downto 0) of STD_Logic; -- 8 element array b(3)
type statcount is array (traffic_light_state) of integers; -- 4 element array s(reset)


- Array literals can be specified by listing values in parentheses or using one of the pattern
shortcuts.

Examples (N is a 4-bit array):
N := (1, 1, 1,1); -- set all elements to character 1
N := (1111); -- set all elements to character 1

Examples (B is a 8-bit array):
B:= (0=>0, 4=>0, others =>1); -- set B=01110111
B:= (0,1,1,1,0,1,1,1); -- set B=01110111

- Array Slice
A subset of an array can be accessed using the array slice functionality. For example, to
only look at sixth to ninth elements of an array M, use one of the following expressions:

M(6 to 9) or M(9 downto 6) -- Element in these arrays are stored in opposite
-- order.

- Concatenation Operator, &
A Concatenation Operator is used to combine (Concatenate) arrays or array elements as
shown by the following examples:

0 & 1 & 1Z results in the string 011Z
B(6 downto 0) & B(7) results in a 1-bit rotate left of the 8-bit array B.

- Unconstrained array
In some application, the designer required an array but at the declaration, its number of
elements or range is unknown. For these applications, array may be declared using the
unconstrained range definition <>. The following example demonstrates the syntax for
declaring a unconstrained range array:
Digital Logic Design Page 194

type type_name is array (type range <>) of element_type;

The most important array type in VHDL is the IEEE 1164 standard user-defined logic type
std_logic_vector which is defined as an ordered set of std_logic bits. If we want to create
unconstrained array of std_logic_vector with an integer index, use the following
declaration:

type STD_LOGIC_VECTOR is array (integer range <>) of STD_LOGIC;

Constant declarations
Constants are used to improve readability, portability and maintainability of the code. Constant name
is typically in capital letters and is descriptive of its use. The constant declaration syntax is shown
below:

constant constant_name : type_name := value;

Below are some examples constant declarations and note the assignment operation is the same as
one used for variable :=:

constant BUS_SIZE: integer := 32; -- Width of component
constant MSB: integer := BUS_SIZE-1; -- Bit number of MSB
constant DEF_OUT : character := Z; -- Default Output constant as character Z

Function definitions
A function is a subprogram that accepts a number of parameters (Parameters must be defined with
mode in ) and returns a result. Each of the parameters and the result must have a pre-determined
type.

Functions may contain local types, constants, variables, nested functions and procedures. All
statements in the function body will be executed sequentially. Below is the simplified syntax of
function definition:

function function-name (
signal_names : signal_type; -- arguments (mode is in)
signal_names : signal_type;
. . .
signal_names : signal_type;
) return return_type is -- one return value which replaces the function
type declaration
constant declaration
variable declaration
function definitions
procedure definitions
begin -- Start of the main body of the function
sequential_statement

sequential_statement
end function_name;

Exampleimplementing A but not B function

entity AbutNotB is
port (X, Y, in BIT; -- X, Y are input of BIT type
Z: out Bit); -- Z is output of BIT type
end AbutNotB
Digital Logic Design Page 195

architecture AbutNotB_arch of AbutNotB

function ButNot (A, B: bit) return bit is -- function definition
begin
if B = 0 then return A;
else return 0;
end if;
end ButNot;

Begin
Z<= ButNot (X,Y); -- function call
end AbutNotB_arch;

Procedure Definitions
A procedure is similar to the function in that it is a subprogram that accepts input parameters but:

A procedure does not have a return values.
A procedures parameters may be constants, signals, or variables, each of whose modes
may be in, out, or inout. This means that by setting the value of the arguments (out, inout),
the value may be returned to the calling program.

Here is the simplified syntax for procedures:

procedure procedure_name ( formal_parameter_list )
procedure procedure_name ( formal_parameter_list ) is
procedure_declarations
begin
sequential statements
end procedure procedure_name;

Example A procedure to implement the functionality of a rising edge-triggered D flip-flop.

procedure dff (signal Clk,Rst,D; in std_ulogic;
signal Q: out std_ulogic) is
begin
if Rst <= 1 then Q <= 0;
elsif rising_edge(Clk) then Q <= D;
end if;
end procedure


Libraries
Similar to other high Level languages, VHDL uses libraries to aggregate already completed
functionality and make it available to designer for reuse. VHDL supplies a number of general libraries
such as IEEE standard libraries and the designer can create local libraries for future use.

The following syntax is used to include a library in a design. This statement should be included prior
to the entity and architecture definitions.

library library_name;

Each of the general VHDL library packages contain definitions of objects that can be used in other
programs. A library package may include signal, type, constant, function, procedure, and component
Digital Logic Design Page 196
declarations.

Once a library is included using the library statement, use statement shown below is used to include
the desired library package in the design.

use package_name

When using VHDL functions, the description of function includes guidance on which library packages
are required for the function.

Example The following two statements brings in all the definitions from the IEEE standard 1164
package:

library IEEE;
use IEEE.Std_Logic_1164.all;

Std_Logic_1164.all contains the following:
- type std_ulogic: unresolved logic type of 9 values;
- type std_ulogic_vector: vector of std_ulogic;
- function resolved resolving a std_ulogic_vector into std_ulogic;
- subtype std_logic as a resolved version of std_ulogic;
- type std_logic_vector: vector of std_logic;
- subtypes X01, X01Z, UX01, UX01Z: subtypes of resolved std_ulogic containing the
values listed in the names of subtypes (i.e. UX01 contains values 'U', 'X', '0', and '1', etc.);
- logical functions for std_logic, std_ulogic, std_logic_vector and std_ulogic_vector;
- conversion functions between std_ulogic and bit, std_ulogic and bit_vector,
std_logic_vector and bit_vector and vice-versa;
- functions rising_edge and falling_edge for edge detection of signals.
- x-value detection functions, is_x, which detect values 'U', 'X', 'Z', 'W', '-' in the actual
parameter.

IEE 1164 Standard Logic Package (released in the 1980s) defines many functions that operate
on the standard types of std_logic and std_logic_vector. IEEE 1164 replaces these proprietary
data types (which include systems having four, seven, or even thirteen unique values) with a
standard data type having nine values, as shown below:

Value Description
'U' Uninitialized
'X' Unknown
'0' Logic 0 (driven)
'1' Logic 1 (driven)
'Z' High impedance
'W' Weak 1
'L' Logic 0 (read)
'H' Logic 1 (read)
'-' Don't-care

These nine values make it possible to accurately model the behavior of a digital circuit during
simulation.

The std_ulogic data type is an unresolved type, meaning that it is illegal for two values (such
as '0' and '1', or '1' and 'Z') to be simultaneously driven onto a signal of type std_ulogic.

If you are describing a circuit that involves multiple values being driven onto a wire, then you
will need to use the type std_logic. Std_logic is a resolved type based on std_ulogic.
Digital Logic Design Page 197
Resolved types are declared with resolution functions.

Example: NAND gate coupled to an output enable
Note: Even though it is not necessary we will use the resolved type std_logic

library ieee;
use ieee.std_logic_1164.all;

entity nandgate is
port (A, B, OE: in std_logic; Y: out std_logic);
end nandgate;

architecture arch1 of nandgate is
signal n: std_logic;
begin
n <= not (A and B);
Y <= n when OE = '0' else 'Z';
end arch1;

Digital Logic Design Page 198
8.6. Operators
This section provides an overview of logical, relational, arithmetic and other operators. Although, this is
an extensive listing, reader is encouraged to explore additional operators through the online
documentation available on the development environment.

Logical operators
The logical operators and, or, nand, nor, xor and xnor are used to describe Boolean logic operations,
or perform bit-wise operations, on bits or arrays of bits.

Operator Description Operand Types Result Types
and And Any Bit or Boolean type Same Type
or Or Any Bit or Boolean type Same Type
nand Not And Any Bit or Boolean type Same Type
nor Not Or Any Bit or Boolean type Same Type
xor Exclusive OR Any Bit or Boolean type Same Type
xnor Exclusive NOR Any Bit or Boolean type Same Type


Relational operators
Relational operators are used to test the relative values of two scalar types. The result of a relational
operation is always a Boolean true or false value.

Operator Description Operand Types Result Type
= Equality Any type Boolean
/= Inequality Any type Boolean
< Less than Any scalar type or discrete array Boolean
<= Less than or equal Any scalar type or discrete array Boolean
> Greater than Any scalar type or discrete array Boolean
>= Greater than or equal Any scalar type or discrete array Boolean


Arithmetic Operations
The Arithmetic operators have been grouped into add/subtract, multiply/divide and sign operators.

Add/Subtract Operators
The adding operators can be used to describe arithmetic functions or, in the case of array types,
concatenation operations.

Operator Description Operand Types Result Type
+ Addition Any numeric type Same type
- Subtraction Any numeric type Same type
& Concatenation Any numeric type Same type
& Concatenation Any array or element type Same array type


Multiply/Divide Operators
These operators can be used to describe mathematical functions on numeric types. It is important
to note that synthesis tools vary in their support for multiplying operators.

Operator Description Operand Types Result Type
* Multiplication Left: any integer or floating point type.
Right: same type
Same as left
* Multiplication Left: any physical type. Same as left
Digital Logic Design Page 199
Right: integer or real type.
* Multiplication Left: integer or real type.
Right: any physical type.
Same as right
/ Division Left: any integer or floating point type.
Right: same type
Same as left
/ Division Left: any integer or floating point type.
Right: same type
Same as left
/ Division Left: integer or real type.
Right: any physical type.
Same as right
mod Modulus Any integer type Same type
rem Remainder Any integer type Same type


Sign Operators
A Sign operator can be used to specify the sign (either positive or negative) of a numeric object or
literal.

Operator Description Operand Types Result Type
+ Identity Any numeric type Same type
- Negation Any numeric type Same type


Other operators
The exponentiation and absolute value operators can be applied to numeric types, in which case they
result in the same numeric type. The logical negation operator results in the same type (bit or
Boolean), but with the reverse logical polarity. The shift operators provide bit-wise shift and rotate
operations for arrays of type bit or Boolean.

Operator Description Operand Types Result Type
** Exponentiation Left: any integer type
Right: integer type
Same as left type
** Exponentiation Left: any floating point type
Right: integer type
Same as left type
abs Absolute value Any numeric type Same as left type
not Logical negation Any Bit or Boolean type Same as left type
sll Shift left logical Left: Any one-dimensional array of Bit or
Boolean
Right: integer type
Same as left type
srl Shift right logical Left: Any one-dimensional array of Bit or
Boolean
Right: integer type
Same as left type
sla Shift left arithmetic Left: Any one-dimensional array of Bit or
Boolean
Right: integer type
Same as left type
sra Shift right arithmetic Left: Any one-dimensional array of Bit or
Boolean
Right: integer type
Same as left type
rol Rotate left Left: Any one-dimensional array of Bit or
Boolean
Right: integer type
Same as left type
ror Rotate right Left: Any one-dimensional array of Bit or
Boolean
Right: integer type
Same as left type

Digital Logic Design Page 200
8.7. Behavioral Design
VHDL design may be conducted using structural or behavioral approach. In structural design, the basic
building blocks are defined using components and the rest of design defines the interconnection between
these components. Structural design is the closest approximation to using the physical component with
wiring diagram. In other words, it is the simply a textual description of a schematic.

The strength of VHDL is based on its ability to compile description of circuit behavior to a fully defined and
implementable design. This is referred to as behavioral design which is much simpler than the structural
design and is commonly used for design.

Behavioral design relies of data flow elements to define functionality which is described in the next
section. Another useful VHDL statement is process:

Characteristics
A process is a list of sequential statements that executes in parallel with other concurrent
statements and processes in the architecture..
Using process, a designer can specify a complex interaction of signals and events in a way that
executes in essentially zero simulated time during the simulation. This characteristic is useful in
synthesizing and modeling combinational or sequential circuits.
A process statement can be used anywhere a concurrent statement can be used.
A process statement has visibility within the scope of an enclosing architecture. This means that
the types, signals, constants, functions and procedures defined in architecture are visible to the
process. But the variable, type, constant, function and procedure defined in the process are not
visible to the architecture.
A process can not declare signals therefore only variable declarations are available in Process.

Syntax of a VHDL process statement

process (signal_name, signal_name, , signal_name)
type declarations
variable declarations
constant declarations
function declarations
procedure declarations
begin
sequential_statement
. . .
sequential_statement
end process;

As a quick reminder, process executes statements sequentially and does not allow signal declaration
within its scope. As discussed earlier, variable assignment operation is := which is different from
signal assignment <=. But the declaration is similar to signal declaration as shown below:

variable variable_names : variable_type;


Process operations
A process is always either running or suspended. The list of signals passed is called the sensitivity
list which determines when the process runs. Below is an overview of process life cycle:

Process is initially suspended.
When any of the signals in the sensitivity list changes value, the process starts execution with
the first sequential-statement in the process.
Digital Logic Design Page 201
Process runs until no other signal in the sensitivity list changes value as a result of running
the process.
In simulation, all the statements in the process execute instantly (no elapsed time from start
to end of the process).

It is possible to write a process that never suspends. For example, a process with X in its sensitivity
list and containing the statement X <= not X. This process will never suspend will continuously
change. This is not a useful process and is similar to infinite loop. Most simulators will detect the
error and terminate after few thousand iterations.

Finally, the sensitivity list is optional; a process without a sensitivity list starts running at time zero in
simulation. One application of such a process is to generate an input waveform for the test bench.

Example Design a prime number detector using process-based data flow architecture.

architecture prime4_arch of prime is
begin
process(N)
variables N3L_N0, N3L_N2L_N1, N3L_N1_N0, N2_N1L_N0: STD_LOGIC;
begin
N3L_N0 := not N(3) and N(0);
N3L_N2L_N1 := not N(3) and not N(2) and N(1);
N3L_N1_N0 := not N(3) and not N(1) and N(0);
N2_N1L_N0 := N2 and not N(1) and N(0);
F <= N3L_N0 or N3L_N2L_N1 or N2L_N1_N0 or N2_N1L_N0;
end process
end prime4_arch;

Note: Within the prime4_arch we have only one concurrent statement and that is the process.


Example Design a Rising Edge D-Flip Flop.

entity ent_DFF is
begin
port(
D, clk, : in std_logic;
Q : out std_logic
);
end ent_DFF;

architecture arc_DFF of ent_DFF is
begin
pdf: process(clk)
begin
if (clk = 1) then
q <= D;
end if;
end process pdf;
end arc_DFF;


Digital Logic Design Page 202
8.8. Dataflow Design Elements
A behavioral design relies on VHDLs dataflow elements in describing the desired behavior. The
remainder of this section is focused on the most commonly used dataflow elements.

Concurrent when signal assignments
Syntax
signal_name <= expression; -- Concurrent signal assignment statement

signal_name <= expression when boolean_expression else -- conditional concurrent
expression when boolean_expression else -- signal assignment statements
. . .
expression when boolean_expression else
expression ;


Example Use the Dataflow elements to write the architecture for the prime number detector
(behavioral design).

architecture prime2_arch of prime is
signal N3L_N0, N3_N2L_N1, N2L_N1_N0, N2_N1L_N0: STD_LOGIC;
begin
N3L_N0 <= 1 when (not N(3) and N(0)) else 0 ;
N3L_N2L_N1 <= 1 when (not N(3) and not N(2) and N(1)) else 0;
N2L_N1_N0 <= 1 when (not N(2) and N(1) and N(0)) else 0;
N2_N1L_N0 <= 1 when (N(2) and not N(1) and N(0)) else 0;
F <= 1 when (N3L_N0 or N3L_N2L_N1 or N2L_N1_N0 or N2_N1L_N0) ;
end prime2_arch;

The prime number detector can also be implemented using conditional concurrent assignment
statements.

Concurrent selected signal assignment
This statement evaluates the given expression when it matches one of the choices, then it assigns
the corresponding signal_value to signal_name.

Syntax

with expression select
Signal_name <= signal_value when choices,
signal_value when choices,
. . .
signal_value when choices,
signal_value when others;

The choices for the entire statement must be mutually exclusive.
The statement with keyword others will be used when none of the other choices matches the
expression results.
Choices may be a single value of expression of a list of values, separated by vertical bars |.

Example Implement a prime number detector using selected signal assignment.

architecture prime3_arch of prime is
begin
with N select
Digital Logic Design Page 203
F <= 1 when 0001,
1 when 0010,
1 when 0011 | 0101 | 0111,
1 when 1011 | 1101,
0 when others;
end prime2_arch;

Sequential If-then-else statement
This sequential statement will give us the ability to make decisions, based on the value of a Boolean-
expression to execute a sequential statement or not.

Syntax of If-then-else statement simple to fully nested

if Boolean-expression then sequential-statement -- do only on true
end if;

if Boolean-expression then sequential-statement -- handle true and false
else sequential-statement
end if;

if Boolean-expression then sequential-statement -- nested if statements
elsif Boolean-expression then sequential-statement

elsif Boolean-expression then sequential-statement
end if;

if Boolean-expression then sequential-statement
elsif Boolean-expression then sequential-statement

elsif Boolean-expression then sequential-statement
else sequential-statement -- catch all else
end if;

Example using If-then-else statements to implement the prime number detector

architecture prime5_arch of prime is
begin
process(N)
variable NI: Integer;
begin
NI :=CONV_INTEGER(N);
if NI=1 or NI=2 then F <= 1;
elsif NI=3 or NI=5 or NI=7 or NI=11 or NI=13 then F <= 1;
else F <= 0;
end if;
end process;
end prime5_arch;

Sequential Case statement
This statement evaluates the given expression, finds a matching value in one of the choices, and
executes the corresponding sequential-statements.

Note: Choice may take multiple values using vertical bar operator |

Syntax
case expression is
Digital Logic Design Page 204
when choices => sequential-statements

when choices => sequential_statements
when others sequential_statements -- do if none of choices match
end case;

Use case statement instead of if-then-else if possible since it is easier to synthesize.

Example Prime number detector using case statement

architecture prime6_arch of prime is
begin
process(N)
begin
case CONV_INTEGER(N) is
when 1 => F <= 1;
when 3 | 5 | 7| 11 | 13 => F <= 1;
when others => F <= 0;
end case;
end process;
end prime6_arch;

Sequential Loop Statements
There are three types of loops that are useful in synthesizing repeated structures.

Sequential Basic Loop Statement syntax
This creates an infinite loop which is useful when doing modeling.

loop
sequential-statement
. . .
sequential-statement
end loop;

Sequential For Loop Statement syntax
the identifier is implicitly declared and will have the same type as the range. The identifier may be
used inside the loop only.

for identifier in range loop
sequential-statement
. . .
sequential-statement
end loop;

The two sequential statements exit and next may be used in the loop body:
exit terminates the loop and continues with the next statement after the loop.
next starts the next iteration through the loop, bypassing the remaining statement in the
current iteration.

Sequential While Loop statement syntax
The identifier is implicitly declared and will have the same type as the range. The identifier may
be used inside the loop only.

while Boolean_expression loop
sequential_statement
. . .
Digital Logic Design Page 205
sequential_statement
end loop;

Digital Logic Design Page 206
8.9. Additional Resources

Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 5 Hardware Description Language
Digital Logic Design Page 207
8.10. Problems

Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.

Digital Logic Design Page 208
Digital Logic Design Page 209
Chapter 9. Commercial Digital Integrated Circuits and Interface Design

9.1. Key concepts and Overview
Output Types
Logic Families
XOR Properties and Applications
Multiplexers and DeMultiplexers (MUXes and DEMUXes)
Adder & Subtractor Design
Multiplier Design
Arithmetic Logic Unit (ALU)
Additional Resources
Problems
Digital Logic Design Page 210
9.2. Output Types
Totem-Pole or Push-Pull Output
Totem-Pole output uses two complementary transistors to force the output to Vcc or ground. The
advantage is that the output is set to one value. Disadvantages are:

- Multiple outputs can not be connected together.
- Circuit is constantly using power since there is a path between Vcc and ground.


Open Collector or Drain Output
This type of output will connect to low voltage when the output is 0, but it is not connected to anything
(High Impedance) when the output is 1. Therefore it needs a pull up resistor to make sure it is
connected to high, otherwise, it is floating resulting in an unknown value.

The advantage of this type of output is that the designer can connect multiple outputs together to
create a wired AND.
IC (TTL)
GND
Internal
Output
Vo
Vcc
IC (CMOS)
GND
Internal
Output
Vo
Vcc
p-Channel
n-Channel
Digital Logic Design Page 211

Open Collector/drain is useful for creating a wired AND by connecting the outputs together and
have one pull up resistor. This is also known as: Virtual AND, Dot-AND or Distributed AND.
Below are three points to consider in relation to this type of configuration:

- When all are high, then the pull up resistor provides the 1 output since all outputs are
open
- If any one of the outputs go low then the output will short to ground and output is 0 (Logic
AND)
- Symbols used to show the Wired-AND are shown below:

.
.
.
&
.
.
.
&
.
.
.
IEC International Symbols for the Function
.
.
.
IEC alternate
Symbol
IEEE alternate
Symbol
&
IC, TTL
GND
Internal
Output
Vo
Vcc
IC (MOS)
GND
Internal
Output
Drain
Collector
Pull up Resistor
required
Vo
Vcc
Pull up Resistor
required
Source
Gate
Is used to indicate an open collector or Drain output
Digital Logic Design Page 212
A wired-OR can be created by using the DeMorgans Theorem: B A B A . = +

Example - Using Wired-OR to implement F= D C B A C B A + + . . . . with the Signal List
SL: F, A, B, C, D.
.


Tri-State, 3-State or High impendence-State Output
An input is used to decide if the output is being driven (enabled).
If the output is enabled, then it behaves like a normal 2-state device
If the output is disabled, then the output has high impedance (referred to as hi-Z).
74LS125 is a good example:

Input Output
OE A F
1 X Z
0 1 1
0 0 0
Notes:
Indicates a 3-state output
A F
OE
A B C D
Wired-AND
F
A
B
A+B
Wired-OR
Vcc Vcc
Digital Logic Design Page 213
- Z indicates high impendence (output is not connected internally)
- X indicates dont care

One of the most common uses of a tri-state output is for a microprocessor memory bus
where you may have multiple memory banks connected but you only want one to be
interacting with the processor at a time.



Microprocessor
Data bus
(bidirectional)
Control bus
(unidirectional)
Address Bus
(unidirectional)
CE_RAM
ADDR RD WR DATA
CE_ROM
ADDR RD DATA
CE_RAM
ADDR RD WR DATA
Decoder
1 0
0 1 2 3
a bits
c bits
d bits
Digital Logic Design Page 214
9.3. Logic Families

TTL (Bipolar Junction Transistor Logic)
First technology to get to market
CMOS (Complementary Metal Oxide Semiconductor)
Used for low power
Integrated-Injection Logic (I
2
L)
Bipolar Transistor and Open-collector output used for the wired-AND function.
Emitter-Coupled Logic (ECL)
High-speed and high-power-requirement solutions.

Digital Logic Design Page 215
9.4. Multiplexer (MUX)/DeMultiplexer (DMUX) Design
Multiplexers (MUX) and DeMultiplexers (DMUX) are used to route signals between networks with unequal
number of signal lines. There are many applications that need one line for control or monitoring, but also
need to analyze the data in a more compressed format. The application can be in communication, power,
control, etc.

For example: You are building a security system that needs to control 200 entry ways. Each entry way
will provide one input (Open/Close). Instead of running the 200 wires to the control, we could DMUX it
into 8-bits (2
n
= 256 when n=8). This means that only 8 lines are needed to go to the control instead of
200.

An example of using a 1 to 8 DMUX and a 8 to 1 MUX


Building a Large Scale MUX from Smaller MUXes
Typically use a cascading tree of MUXes to build a larger MUX :
Identify the number of MUX-ed outputs needed:
n {ln(#input lines} / {ln 2} where n is the smallest integer that satisfies the equation and
indicates the number of outputs.
If you have J-to-K MUX available then you will need n/K levels

Example of implementing a 4-to-1 MUX using 2-to-1 MUXes
MUX
D
0
_i
D
1
_i
S
0
S
1
S
2

DMUX
The signal can be used for
computation or reduce the
number of wires required to
communicate
Output Input
Connect one of D0-D7 to output
D
2
_i
D
3
_i
D
4
_i
D
5
_i
D
7
_i
D
6
_i
D
0
_o
D
1
_o
D
2
_o
D
3
_o
D
4
_o
D
5
_o
D
7
_o
D
6
_o
S
0
S
1
S
2

Selects the input line that will be
connected to the output.
Selects the output line that will be
connected to the input.
Digital Logic Design Page 216



Example of implementing a 256-to-1 MUX using 8-to-1 MUXes.

Diagram of 256 to 1 MUX.

Diagram of a 256-to-1 MUX using 8-to-1 MUXes:
F
D
0

D
255

.
.
.
S
0

S
7

D0
D1
S
0
1
D2
D3
S
0
1
S
0

S
0

S
0
1
S
1

Cascade Level 2 Cascade Level 1
F
Digital Logic Design Page 217

D248
D255
S
0

7
Cascade Level 1 Cascade Level 2
. . .
0
1
2
D0
D7
S
S
0
S
1
S
2

0

7
. . .
0
1
2
.
.
.
S
0

7
0
1
2
.
.
.
Out 0
Out 31
S
0

7
0
1
2
S
0
3
7
0
1
2
Cascade Level 3
F
F0
F3
S
0
S
1
S
2

S
3
S
4
S
5

S
3
S
4
S
5

S
6
S
7
Gnd
Digital Logic Design Page 218
Larger DMUX from smaller DMUX
1-to-2 DMUX Design & Symbol

The larger DMUX can be built from smaller DeMUXes by cascading the DeMUXes similar to
MUXes.
For example: building a 3-to-8 DMUX using 1-to-2 DeMUXes:


Y
X
W
0
1
2
EN DS
0
1
2
3
4
5
6
7
Cascade Level 2 Cascade Level 1
EN
0
D
0

D
1

0

1
EN
0
D
14

D
15

0

1
Z
.
.
.
DS
Data Select
D
0

D
1

A
0

encoded data
EN
0
D
0

D
1

DS
A
0

0

1
Digital Logic Design Page 219
9.5. Adder & Subtractor Design

Small adders can be shown at gate level, but for larger designs we will use an iterative modular design
process. This process allows us to define a circuit for the i
th
module, and then use it to show the overall
design without redrawing the circuit each time.

Half Adder
A Half Adder is the simplest form of an adder. It simply treats the carry and binary bit-addition
separately.
Example: 1-bit adder

Half Subtractor
A Half Subtractor is the simplest form of Subtractor circuit.
Example: 1-bit Subtractor


Note: The Half Subtractor is the same as the Half Adder except for one input inversion.
Universally, Subtractor are created by adding additional circuitry to an adders.
Full Adder
A Full Adder is a set of single bit adders combined to make an nbit adder. It accepts a carry
from a lower-significant-digit adder and produces a carry to be used by the next-higher-
significant-digit adder.
Example:1-bit full adder module design for i
th
bit.

A
0
Minuend
- B
0
Subtrahend

_______
BO
1
D
0

Borrow Out
(AND)
Difference Bit
Mod 2 (XOR)
A
0
B
0
B0
1
D
0

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Half Subtractor Process
Truth Table
A
0

B
0

D
0

BO
1

Gate-level Logic Circuit
A
0

B
0

A
B
S
S
0

CO CO
1

HS
Half Subtractor Symbol
A
0

+ B
0
_______
CO
1
S
0

Carry Out
(AND)
Sum Bit
Mod 2 (XOR)
A
0
B
0
C0
1
S
0

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Half Adder Process
Truth Table
A
0

B
0

S
0

CO
1

Gate-level Logic Circuit
A
0

B
0

A
B
S
S
0

CO CO
1

HA
Half Adder Symbol
Digital Logic Design Page 220


Ripple-Carry Adder (RCA)
A Ripple-Carry Adder uses Full Adders in a cascading form. The carry from one adder is fed to
the next most significant bit-adder.

The Ripple-Carry Adder will have to wait until all the carries have propagated through the
circuit before output stabilizes and results are valid. Carry-Look-ahead or carry-anticipation is
often used to speed up the addition.

Indirect Subtraction
Given the following facts, a Subtractor can be designed from an RCA:
Given A B = A + (-B)
From the twos complement, (-B)
2RC
= 1 + B
Use an XOR to invert B when SUB=1 (subtraction) and B when SUB=0 (addition).
A B CI
S
0

FA0
CO S
A0 B0 CI
A B CI
S
1

FA1
CO S
A1 B1 CI
A B CI
S
2

FA2
CO S
A2 B2 CI
A B CI
S
3

FA3
CO S
A3 B3 CI
CO
Overflow
GND
CI Carry In
A

Operand 1
+ B

Operand 2

________
CO S
0

Carry Out
Sum Bit
CI A B C0 S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Full Adder Process
Truth Table
CI
A
0

B
0

CI
A
B
S
S
0

CO CO
1

FA
Full Adder Symbol
0 0
1 1
0 1
0 1
CI, A
B
0 1
00
01
11
10
Carry Out CO =
A.B + CI.A + CI.B
0 1
0 1
1 0
1 0
B
0 1
00
01
11
10
Sum Bit S = C B A
CI, A
CI
A
B
S
CO
Full Adder Circuit
Digital Logic Design Page 221


Carry-Anticipation or Carry Look-Ahead Adder
This solution reduces the settling time of adders.
Ripple-Carry for an n-bit adder will have settling time of 3t
p
+ 2(n-1)t
o
since each stage will
generate an output based on the last stage and would require 2t
p
(Gate propagation) to
complete the result.
Carry-Look-Ahead basically adds the circuitry to calculate the carry without having to wait for
the propagation from each stage, effectively cutting the settling time to 6t
p
for an n-bit adder
when n>2. For a 1-bit adder, the setting time is 3t
p
, and for a two-bit adder, the settling time is
4t
p
.

Carry-Save Adders
Carry-Save Adders (CSAs) are designed to add more than two operands.
CSAs are designed using Full Adders (FA)
- The carry from one level is fed into the next significant bit of the next stage.
- The last stage shifted by one to the left but no new output is generated.
- The number of rows of Adders = (The number of operands to be added) - 1
Example (five operands):

A0 Operand 1
B0 Operand 2
+ C0 Operand 3
----------- .
S10 Sum, Row 1
CO11 Carry Row 2 (carry Save)
+ D0 Operand 4
--------------- .
S21 S20 Sum, Row 2
CO21 Carry Row 3 (carry Save)
+ E0 Operand 5
--------------- .
S31 S30 Sum, Row 1
CO32 CO31 Carry Row 4 (carry Save)
+ CO43 CO42 CO41 Carry Row 4 (no carry Save)
----------------------------------- .
S43 S42 S41 S40 Sum, Row 4 (Last Row)

A B CI
S
0

FA0
CO S
A0 B0 SUB
A B CI
S
1

FA1
CO S
A1 B1
A B CI
S
2

FA2
CO S
A2 B2
A B CI
S
3

FA3
CO S
A3 B3
CO
Overflow
Digital Logic Design Page 222





A B CI
FA
CO S
A0 B0 C0
A B CI
FA
A1 B1 CI
A B CI
FA
A2 B2 C2
A B CI
FA
A3 B3 C2
GND
. . .
A B CI
FA
A B CI
FA
A B CI
FA
A B CI
FA
CO S
CO S CO S CO S
CO S CO S
CO S
. . .
D3 D2 D1
D0
.
.
.
.
.
.
.
.
.
.
.
.
A B CI
FA
A B CI
FA
A B CI
FA
CO S CO S CO S
S0
GND
S1 S2 S3
Last Row
Row 2
Row 1
Digital Logic Design Page 223
9.6. Multiplier Design
First some basics of multiplication:
There are two methods to implement the above multiplication operation.
Multiplier Design using 2-operand Adders
Multiplier Design using Multiple-Operand Adder

A
m
A
2
A
1
A
0
Multiplicand (m bits)
B
n
B
2
B
1
B
0
Multiplicand (n bits)
_____________________

X X X X X Partial Product 0
X X X X X Partial Product 1
.
.
.
X X X X X Partial Product n
______________________
R(m+n) R
2
R
1
R
0
Result (m+n bits)

Truth-table for a 2-bit by 2-bit multiply
A1 A0 B1 B0 R3 R2 R1 R0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1
Digital Logic Design Page 224
9.7. Arithmetic Logic Unit (ALU) Design

The Arithmetic Logic Unit (ALU) is the heart of the computational capability of a computer.

A typically ALU Block Diagram (74LS382) is shown below:

S2 S1 S0 Output: F and CO
0 0 0 Clear
0 0 1 B
minus
A
0 1 0 A
minus
B
0 1 1 A
plus
B
1 0 0 A
XOR
B
1 0 1 A
or
B
1 1 0 A
and
B
1 1 1 PRESET

A
B
CI M
S1
CO
F
ALU
3
3
3
S0 S2
Digital Logic Design Page 225
9.8. Additional Resources

Wakerly, I. Digital Design. (2006) Prentice Hall
Chapter 4 & 6, Combinational Logic Design Principles & Combinational Logic Design Practices
Digital Logic Design Page 226
9.9. Problems

Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.


Digital Logic Design Page 227
Appendix A. Additional Resources
Additional resources are available at the authors website www.EngrCS.com