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AVR Instruction Set Summary

This document provides a summary of the AVR instruction set. It includes a table listing the mnemonic, operands, description, operation, registers used, constants used, flags affected, clock cycles, and word width for each instruction type. The instruction types covered include arithmetic and logic instructions, branch instructions, data transfer instructions, and bit and bit-test instructions.

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colea11
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103 views3 pages

AVR Instruction Set Summary

This document provides a summary of the AVR instruction set. It includes a table listing the mnemonic, operands, description, operation, registers used, constants used, flags affected, clock cycles, and word width for each instruction type. The instruction types covered include arithmetic and logic instructions, branch instructions, data transfer instructions, and bit and bit-test instructions.

Uploaded by

colea11
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

AVR Instruction Set Summary

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Mnem.

Oper.

Description

ARITHMETIC AND LOGIC INSTRUCTIONS


ADD
Rd, Rr Add two Registers
ADC
Rd, Rr Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr Subtract with Carry two Reg.
SBCI
Rd, K
Subtr. with Carry Const. from Reg.
SBIW
Rdl,K
Subtract Immediate from Word
AND
Rd, Rr Logical AND Registers
ANDI
Rd, K
Logical AND Register and Const.
OR
Rd, Rr Logical OR Registers
ORI
Rd, K
Logical OR Register and Const.
EOR
Rd, Rr Exclusive OR Registers
COM
Rd
Ones Complement
NEG
Rd
Twos Complement
SBR
Rd,K
Set Bit(s) in Register = ORI
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
MUL
Rd, Rr Multiply Unsigned
MULS
Rd, Rr Multiply Signed
MULSU Rd, Rr Multiply Signed with Unsigned
FMUL
Rd, Rr Fractional Multiply Unsigned
FMULS Rd, Rr Fractional Multiply Signed
FMULSU Rd, Rr Fract. Mult. Signed with Unsigned
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
JMP
k
Direct Jump
RCALL k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
CALL
k
Direct Subroutine Call
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Imm.
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Br. if Greater or Equal, Signed
BRLT
k
Br. if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Br. if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Br. if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled

wdr 03.03.03

Operation

Reg. Const. Flags

Rd = Rd + Rr
Rd = Rd + Rr + C
Rdh:Rdl = Rdh:Rdl + K
Rd = Rd - Rr
Rd = Rd - K
Rd = Rd - Rr - C
Rd = Rd - K - C
Rdh:Rdl = Rdh:Rdl - K
Rd = Rd Rr
Rd = Rd K
Rd = Rd v Rr
Rd = Rd v K
Rd = Rd xor Rr
Rd = $FF - Rd
Rd = $00 - Rd
Rd = Rd v K
Rd = Rd ($FF - K)
Rd = Rd + 1
Rd = Rd - 1
Rd = Rd Rd
Rd = Rd xor Rd
Rd = $FF
R1:R0 = Rd x Rr
R1:R0 = Rd x Rr
R1:R0 = Rd x Rr
R1:R0 = (Rd x Rr) << 1
R1:R0 = (Rd x Rr) << 1
R1:R0 = (Rd x Rr) << 1

0-31
0-31
24-30
0-31
16-31
0-31
16-31
24-30
0-31
16-31
0-31
16-31
0-31
0-31
0-31
16-31
16-31
0-31
0-31
0-31
0-31
16-31
0-31
16-31
16-23
16-23
16-23
16-23

PC = PC + k + 1
PC = Z
PC = k
PC = PC + k + 1
PC = Z
PC = k
PC = STACK
PC = STACK
if (Rd = Rr) PC = PC+2 or 3
Rd - Rr
Rd - Rr - C
Rd - K
if (Rr(b)=0) PC = PC+2 or 3
if (Rr(b)=1) PC = PC+2 or 3
if (P(b)=0) PC = PC+2 or 3
if (P(b)=1) PC = PC+2 or 3
if (SREG(s) = 1) then PC=PC+k+1
if (SREG(s) = 0) then PC=PC+k+1

if (Z = 1) then PC = PC+k+1
if (Z = 0) then PC = PC+k+1
if (C = 1) then PC = PC+k+1
if (C = 0) then PC = PC+k+1
if (C = 0) then PC = PC+k+1
if (C = 1) then PC = PC+k+1
if (N = 1) then PC = PC+k+1
if (N = 0) then PC = PC+k+1
if (N xor V= 0) then PC = PC+k+1
if (N xor V= 1) then PC = PC+k+1

if (H = 1) then PC = PC+k+1
if (H = 0) then PC = PC+k+1
if (T = 1) then PC = PC+k+1
if (T = 0) then PC = PC+k+1
if (V = 1) then PC = PC+k+1
if (V = 0) then PC = PC+k+1
if ( I = 1) then PC = PC+k+1
if ( I = 0) then PC = PC+k+1

AVR Instruction Set Summary

0-31
0-31
0-31
16-31
0-31
0-31
0-31
0-31

#W. #Clk

Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C

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2

2K None
None
0-4M None
2K None
None
0-4M None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
0-255 Z, N,V,C,H
None
None
None
None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None
64 None

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1
1
1

2
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4 [5]
4
4
1/2/3
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1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
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1/2
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1/2
1/2
1/2
1/2
1/2
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1/2
1/2
1/2
1/2
1/2
1/2
1/2

0-63
0-255
0-255
0-63
0-255
0-255

1/3

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Mnem.

Oper.

Description

ARITHMETIC
AND INSTRUCTIONS
LOGIC INSTRUCTIONS
DATA
TRANSFER
MOV
Rd, Rr Move Between Registers
MOVW Rd, Rr Copy Register Word
LDI
Rd, K
Load Immediate
LD
Rd, X
Load Indirect
LD
Rd, X+ Load Indirect and Post-Inc.
LD
Rd, -X Load Indirect and Pre-Dec.
LD
Rd, Y
Load Indirect
LD
Rd, Y+ Load Indirect and Post-Inc.
LD
Rd, -Y Load Indirect and Pre-Dec.
LDD
Rd,Y+q Load Indirect with Displacement
LD
Rd, Z
Load Indirect
LD
Rd, Z+ Load Indirect and Post-Inc.
LD
Rd, -Z
Load Indirect and Pre-Dec.
LDD
Rd, Z+q Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr Store Indirect and Post-Inc.
ST
-X, Rr
Store Indirect and Pre-Dec.
ST
Y, Rr
Store Indirect
ST
Y+, Rr Store Indirect and Post-Inc.
ST
-Y, Rr
Store Indirect and Pre-Dec.
STD
Y+q,Rr Store Indirect with Displacement
ST
Z, Rr
Store Indirect
ST
Z+, Rr
Store Indirect and Post-Inc.
ST
-Z, Rr
Store Indirect and Pre-Dec.
STD
Z+q,Rr Store Indirect with Displacement
STS
k, Rr
Store Direct to SRAM
LPM
Load Program Memory
LPM
Rd, Z
Load Program Memory
LPM
Rd, Z+ Load Progr. Mem. and Post-Inc
ELPM
Extended Load Program Memory
ELPM
Rd, Z
Extended Load Program Memory
ELPM
Rd, Z+ Ext. Load Progr. Mem. and Post-Inc
SPM
Store Program Memory
IN
Rd, P
In Port
OUT
P, Rr
Out Port
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
CBI
P,b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left Through Carry
ROR
Rd
Rotate Right Through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Twos Compl. Overflow.
CLV
Clear Twos Compl. Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half Carry Flag in SREG
CLH
Clear Half Carry Flag in SREG

wdr 03.03.03

Operation

Reg. Const. Flags

Rd = Rr
Rd+1:Rd = Rr+1:Rr
Rd = K
Rd = (X)
Rd = (X), X = X + 1
X = X - 1, Rd = (X)
Rd = (Y)
Rd = (Y), Y = Y + 1
Y = Y - 1, Rd = (Y)
Rd = (Y + q)
Rd = (Z)
Rd = (Z), Z = Z+1
Z = Z - 1, Rd = (Z)
Rd = (Z + q)
Rd = (k)
(X) = Rr
(X) = Rr, X = X + 1
X = X - 1, (X) = Rr
(Y) = Rr
(Y) = Rr, Y = Y + 1
Y = Y - 1, (Y) = Rr
(Y + q) = Rr
(Z) = Rr
(Z) = Rr, Z = Z + 1
Z = Z - 1, (Z) = Rr
(Z + q) = Rr
(k) = Rr
R0 = (Z)
Rd = (Z)
Rd = (Z), Z = Z+1
R0 = (RAMPZ:Z)
Rd = (RAMPZ:Z)

0-31
0-30
16-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31

0-31
0-31

(Z) = R1:R0
Rd = P
P = Rr
STACK = Rr
Rd = STACK

0-31
0-31
0-31
0-31

I/O(P,b) = 1
I/O(P,b) = 0
Rd(n) = Rd(n+1), Rd(7) = 0
Rd(0)=C,Rd(n+1)=Rd(n),C=Rd(7)
Rd(7)=C,Rd(n)=Rd(n+1),C=Rd(0)

Rd(n) = Rd(n+1), n=0..6


Rd(3..0)=Rd(7..4),Rd(7..4)=Rd(3..0)

SREG(s) = 1
SREG(s) = 0
T = Rr(b)
Rd(b) = T
C=1
C=0
N=1
N=0
Z=1
Z=0
I=1
I=0
S=1
S=0
V=1
V=0
T=1
T=0
H=1
H=0

AVR Instruction Set Summary

0-63

0-63
0-64K

0-63

0-63
0-64K

0-31
0-31

Rd = (RAMPZ:Z), RAMPZ:Z = RAMPZ:Z+1

Rd(n+1) = Rd(n), Rd(0) = 0

0-255

0-31
0-31
0-31
0-31
0-31
0-31

0-31
0-31

0-63
0-63

None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None

0-31 None
0-31 None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H

#W. #Clk
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1

1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
1
1
2
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2/3

a
x
x
x

b
x
x
x

c
x
x
x

Mnem.

x
x
x
O

ARITHMETIC
AND
LOGIC INSTRUCTIONS
MCU
CONTROL
INSTRUCTIONS
NOP
No Operation
SLEEP
Sleep
WDR
Watchdog Reset
BREAK
Break

Oper.

Description

Operation

(see specific descr.)


(see specific descr.)
For On-chip Debug Only

Reg. Const. Flags


None
None
None
None

#W. #Clk
1
1
1
1

1
1
1
N/A

Anmerkungen:
a,b,c,d: Einschrnkungen:
a: Tiny 11, 12, 15, 28; 90S1200
b: Tiny 26; alle 90Sxx auer 90S1200
c: Mega 103
d: Mega 8, 16, 32, 64, 161, 162, 163, 323, 8515
alle Befehle bei Mega 128
X = Befehl bei allen AVRs der Gruppe vorhanden, O = nur bei manchen der Gruppe vorhanden
Reg.:
Const.:
#W:

mgliche Register (alle Word-Befehle nur mit geraden Registern)


Konstanten-Bereich (bei Befehls-Adressen und -Displacements in Words)
Anzahl Befehlsworte

#Clk:

Anzahl Takte
bei 2 Werten: kein Sprung / Sprung
bei 3 Werten: kein Skip / Skip ber 1 Word / Skip ber 2 Words
bei CALL: 4 Takte bei 16 Bit breitem PC, 5 Takte bei 22 Bit breitem PC (keiner der aktuellen AVRs)

wdr 03.03.03

AVR Instruction Set Summary

3/3

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