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Muhammad Rafay Abdullah Roll# 038: Lab# 5 Submitted To: Sir Faheem

This document contains code for two Verilog modules: 1) An adder/subtractor module (au) that performs different operations on inputs a and b based on the values of selection inputs s0, s1, and cin. 2) A logic unit module (lu) that performs AND, OR, XOR, and NOT operations on inputs a and b based on the values of selection inputs s0 and s1. Stimulus modules are also provided to test each logic module by changing the selection input values over time.

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47 views

Muhammad Rafay Abdullah Roll# 038: Lab# 5 Submitted To: Sir Faheem

This document contains code for two Verilog modules: 1) An adder/subtractor module (au) that performs different operations on inputs a and b based on the values of selection inputs s0, s1, and cin. 2) A logic unit module (lu) that performs AND, OR, XOR, and NOT operations on inputs a and b based on the values of selection inputs s0 and s1. Stimulus modules are also provided to test each logic module by changing the selection input values over time.

Uploaded by

mtkhusro92
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Muhammad Rafay Abdullah

Roll# 038
Lab# 5
Submitted to:
Sir Faheem

Q1:
Main:
module au(a,b,s0,s1,cin,out);

input [3:0] a,b;


input s0,s1,cin;
output reg [3:0]out;

always@(a,b,s0,s1,cin)
begin

case({s1,s0,cin})
3'b000: out = a;
3'b001: out = a;
3'b100: out = a+b;
3'b101: out = a+b+1;
3'b010: out = a+(~b);
3'b011: out = a-b;
3'b110: out = (~a)+b;
3'b111: out = b-a;

endcase
end

endmodule

Stimulus:
module au_stim;
reg [3:0] a,b;
reg s0,s1,cin;
wire [3:0]out;

au aa(a,b,s0,s1,cin,out);

initial
begin

a = 4'b0101;
b = 4'b0010;
s0 = 0;
s1 = 0;
cin = 0;

#20
s0 = 0;
s1 = 0;
cin = 1;

#20
s0 = 0;
s1 = 1;

cin = 0;

#20
s0 = 0;
s1 = 1;
cin = 1;

#20
s0 = 1;
s1 = 0;
cin = 0;

#20
s0 = 1;
s1 = 0;
cin = 1;

#20
s0 = 1;
s1 = 1;
cin = 0;

#20
s0 = 1;
s1 = 1;

cin = 1;

end
endmodule

Q2:
Main:
module lu(a,b,s0,s1,out);

input [3:0] a,b;


input s0,s1;
output reg [3:0]out;

always@(a,b,s0,s1)
begin

if(s1==0&&s0==0)
out = a&b;
else if(s1==0&&s0==1)
out = a|b;
else if(s1==1&&s0==0)
out = a^b;
else if(s1==1&&s0==1)
out = ~a;

end

endmodule

Stimulus:
module lu_stim;

reg [3:0] a,b;


reg s0,s1;
wire [3:0]out;

lu aa(a,b,s0,s1,out);

initial
begin

a = 4'b0101;
b = 4'b0010;
s0 = 0;
s1 = 0;

#20
s0 = 1;
s1 = 0;

#20

s0 = 0;
s1 = 1;

#20
s0 = 1;
s1 = 1;

end
endmodule

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