Reset: Line Vreg Voltage
Reset: Line Vreg Voltage
+12V
10
11
12
13
14
15
16
17
18
19
20
+5V
C3
U1
LM7805CT
LINE VREG
VOLTAGE
COMMON
J1
C2
C1
10F
0.33F
0.1F
HDR1X2
VDD
SWIM
GND
NRST
+5V
R1
10k
+5V
HDR1X4
Reset
J2
C4
0.1F
Right
Down
E
Left
+5V
+5V
U3
+5V
C5
C6
1F
0.1F
1
2
3
4
5
6
7
8
9
10
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
UART1_TX/AIN5/(HS) PD5
UART1_RX/AIN6/(HS) PD6
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
[SPI_NSS] TIM2_CH3/(HS) PA3
C7
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2 (HS)/AIN3/[TIM2_CH3]
PD1(HS)/SWIM
PC7 (HS)/SPI_MISO [TIM1_CH2]
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
PB4 (T)/I2C_SCL [ADC_ETR]
PB5 (T)/I2C_SDA [TIM1_BKIN]
20
19
18
17
16
15
14
13
12
11
R8
10k
R9
R10
S5A
Key = A
Centre
+5V
R5
R4
10k
10k
S3A
S2A
Key = A
Key = A
Up
+5V
+5V
E
R3
R2
10k
10k
S1A
S4A
Key = A
Key = A
STM8S003F3
1F
G
10
11
12
13
14
15
16
17
18
19
20