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BInary Multiplier PDF

The document describes a Verilog code for a 4-bit binary multiplier circuit. It includes modules for a half adder, full adder, and a top level 4x4 bit multiplier module. It also includes a test bench module that applies sample inputs and shows the output in decimal and hexadecimal formats.

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Ramesh Varma
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49 views6 pages

BInary Multiplier PDF

The document describes a Verilog code for a 4-bit binary multiplier circuit. It includes modules for a half adder, full adder, and a top level 4x4 bit multiplier module. It also includes a test bench module that applies sample inputs and shows the output in decimal and hexadecimal formats.

Uploaded by

Ramesh Varma
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BINARY MULTIPLIER:-

Verilog Code:-

module hd(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule

module fd(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule

module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
assign product[0] = (inp1[0]&inp2[0]);
hd hd1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
fd fd1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
fd fd2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
hd hd2(x6,x7,(inp1[1]&inp2[3]),x5);
hd hd3(product[2],x15,x2,(inp1[2]&inp2[0]));

fd fd5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
fd fd4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
fd fd3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
hd hd4(product[3],x12,x14,(inp1[3]&inp2[0]));
fd fd8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
fd fd7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
fd fd6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule

Text Bench:module stimulus_v;


reg [3:0] inp1;
reg [3:0] inp2;
wire [7:0] product;
multiply4bits a1(product,inp1,inp2);
initial begin
inp1 = 4'b1000;
inp2 = 4'b1001;
#2 $stop;
end
endmodule

SIMULATION:Hexadecimal:-

Decimal:-

RTL SCHEMATIC:-

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