SECTION " ut W vn FIGURE K TABLE OF CONTENTS ume GENERAL DESCRIPTION 1/0 PIN DESCRIPTION MEMORY ALLOCATION CRU ALLOCATION INTERRUPT HANDLING ELECTRICAL CHARACTERISTICS aLossany LIST OF ILLUSTRATIONS TITLE 99/4 SYSTEM BLOCK OTAGRAH 1/0 READ TIMING 1/0 WRITE TIMING RU TIMING CONNECTOR PIN IDENTIFICATION DIAGRAM 99/4 LOGIC BOARD COMPONENT LOCATION DIAGRAM 99/4. SCHEMATIC DIAGRAM i PAGE fen an 12 16GENERAL DESCRIPTION The concept far the Texas Instrumente Home Computer 99/4 1/0 bus is to provide maximum flexibility and good performance within a constraint of low cost for both mainframe and computer system. This concept 1s achieved by providing both memory and CRU I/O buses to the 99/4 peripherals. ‘This brief description will give key details of this intecface. Detailed information regarding the 9900 CPU is assumed. A source for this information is the 9900 Family Systems Design and Data Book. This manual may be obtained from I Semiconductor Distribers. The memory bus (with data bus converted to eight bits wide) is used for instruction fetch from ROM in external peripherals and Cor date transfer tu/from memory mapped portions of these devices. | The CRU bus is used for peripheral enable/disable and for device control and data transfer ra/fram CRM mapped peripherals. A block diagram of the 72 99/4 electronics is shown in Figure A. The TMS 9900 microprocessor accesses each peripheral to obtain instructions from the device service routine (DSR) read only memory. Since each peripheral contains its own DOR; the 99/4 does not have to be designed to anticipate future peripheral requirements. ‘he dual 1/0 bus capability, along with interupt handling and external DSR's provide flexibility at low cost.WWYOVIC 49074 NALSAS 1/66 fswow singoW 3ingow Hgaads agaaas awuciiiggy| | o3HINAS 39vJUaiNI 1 “NWO WOH WO WVU wusHl¥ad atnaow anvwnio9 sna o/ = LVS G10S | SID2135 j RTWuvd) ecog AUONIN_siv-OV MD \ i ‘3vauaini] [savswaLn| Gevogaay) | waiisaor|| 311 35S¥9| AaN OF anal wOLYUINaD HNIOS X30] K+ ULNOD O/T 9 1066 SL nvow T 7 s 3OVSuaLNI YI walvaANoa sng sansa sue aw wOLaus| a WOLNVED “WALNI] r ase SL Saute! | | BL eszi| NNALSAS| ioou woss:90ud0uDIWW 118-3 ZNW ‘0006 SHU voLINOW w0109 £1 waAtda 130791/0 PIN DESCRIPTION SIGNATURE PIN ag csp) AL az aa. ad AS AG AT Ag ag Alo All al2 Al3 ala A1S/CROOUT pg (msB) pL D2 Da D4 DS Dé D7 MEMEN DBIN ‘CROCEK cRUIN aa 30 20 io i 5 29 17 14 18 6 8 ul 15 16 1g 37 40 39 42 35 38 36 34 32 26 28 22 33 10 out out out out Out Out Out out Out out core Out out, out, Out Out 1/0 1/0 1/0 1/0 1/0 1/90 1/0 17o out out out out, out In DESCRIPTION ADDRESS BUS AQ through A1S comprise the address bus. This bus pro- vides the 16 bit memory add- ress vector to the external memoxy system when MEMEN io active. Address bit 15 is also used for CRU DATA OUT on Rit output instructions. DATA Bue DO through D7 comprise the bidirectional data bus. This bus transferes memory data to (when writing) and from (when reading) the ex- ternal wewury system when MEMEN is active. BuS_cownent MEMory ENable. WEMEN in- dicates a memory access. Data Bus In. Wnen active (high) the data buffers and 9900 are in the_input mode. Write ENable. WE indicates a memory write. ae Memory Block Enable. MBE indicates a memory access in memory block 4000-5PFF. CRU Clock. Indicates data is available on the CRU OUT Line. cRU ‘data IN. Input data line to the Home Computer.1/0 PIN DESCE SIGNATURE LZYLOW (CONTINUED) am 10 prapy/HOLD 12 In HOLDA/TAQ od EXT INT | AUDIO IN 41 Out 1300 In 3 Out 4 tn 24 Out 21,23 as,27 2 out 440otn DESCRIPTION MEMORY CONTROL READY (when MEMEN is active) {ndicates external memory is ready for a memory access. HOLD ( when MEMEN is ine active! indicates a request to use the data bus. HOLD Acknowledge goes true when MEMEN is inactive and {ndicates Lhat the 9900 is in a HOLD state. tnctructinn AcQuisition in- dicates (when MEMEN is active) the CPU is acquir- ing an instruction during @ memory cycle. ‘TIMING AND CONTROL when active, LOAD cuases the Cpu to execute a nonmaskable interrupt with memory add- rass FFFC containing tne trap vector. hen active, RESE” causes the Home Computer and the perinh- érais to be reset. Will be held active for a minimum of § clock cycles. External INTerrupt. When active, EX" INT causes the Cpu to execute an interrupt. GU Clock. Phase 2 of the cpu clock. eer ee ee ee POWER Ground reference. SPEECH MODULE SIGNALS speech Block Enable. Sa in- dicates a memory access in the speech memory. Tnpue for the audio Erom the h module.45 “5 es 8000 8400 8800 ooo 8coo acoz 9000 3400 9800 5 9802 3coo 9co2 set Core Tet 2 5 funaig Gren Pit if ADDRESSES AO Al a2 A3 Ad AS 1 Supply vultage (+5v Nom) for speech module (S0ma Max} 43 Supply voltage (-5v Nom) for speech madule ($0ma Max) Ir, MEMORY ALLOCATION The memory address space 1s broken into 8 blocks of SR bytes of memory. ‘The third block (addresses 4000 - SFFF) is predecoded and made available at the 1/0 port for the peripherals. the sivche Seventh and eighth block (addresses A000 - FFEF) are available for future expansion. For the speech module, (addresses 9000 - 97FF), a predecaded line is avaliaple at the 1/0 port, SYSTEM MEMORY MAP EEX ADDRESS igmaw > 0 = LFPF Console ROM spare vod - 3FFP Future Expansion (internal/console) ee aa * 4000 - SFFF = Peripheral expansion (predecoded to 1/0 Connector) ates oil 3 * 6000 - 7rrr Game ‘cartriage ROM/RAM (predecoded to GROM Connector) fue jy y —7 8000 - SFFF Microprocessor RAM, VDP, GROM, SOUND and SPEECH oclect. A000 - BFFF Future Expansion C000 - DFFF Future Expansion : 2000 - FFFF Future Expansion MEMORY MAPPED DEVICES Ala ALS USE ee a Internal RAM (8300~83FF) Sound VDP Read Data VDP Read Status VDP Write Data VDP Write Address speech Read Speech Write GROM Read Data GROM Read Addrecs GROM Write Data GROM Write Address Me ne e@cccescccce o e@cccc0cecce o HEHEHHeecce o HoH HoeHH EHO © c0cecccccceIv. cpu ALLOCATION Of the available 4K of CRU bits, the first 1 (addresses 0000-07FE) are used internally in the Home Computer. The second 14 (addresses 0800-0rrz) are reserved for future use. The last 2% (addresses 1000-1FFE) are reserved for the peripherala to be plugged in the 1/0 part. siock 6£ 128 CRU bits is assigned to each peripheral as listed below. CRU_ASSIGNMENTS cru ADDRESSES a3 A¢ AD AG AT © UGE anno-arFR of x xX X X INTERNAL USE 1000-10FE 1 0 0 0 0 RESERVED 1100-11FE 1 0 0 0 1 DISK CONTROLLER 1200-12FE 1 0 0 1 0 RESERVED _ 1300-13FE Log uo L 1 Re 232 (1) 1400-14FE 1 9 L 0 0 RESERVED 1500-15FE 1 0 1 0 1 Rs 232 (11) igoo-tcrs 1 0 2 1 0 RESERVED 1700-17F— 1 0 1 1 1 RESERVED igoo-isrE 1 1 0 0 0 THERMAL PRINTER 1900-1FFE 1 1 X X X FUTURE EXPANSION INTERRUPT RANDLT whe intercupt available on the 1/0 port is one of the maskable interrupts of the TMS 9901 Programmable Systems Interface. 2900 INTERRUPTS VECTOR Loc. INTERRUPT (MEMORY ADDR. CPU DEVICE LEVEL IN HEX) BIN ASSIGNMENT (High 0000 RESET RESET est 9 FFFC LOAD. LOAD Prior 1 0004 INTL EXT DEV (9901) ity) bower priority CPU interrupts are not used. The additional interrupts available are implemented on 9901.ADDRESS CRU BIT 0000 9002 oo4c 0006 0008 00a oooc 000g vuLu 0012 0014 ants ols OOlA-1E ADDRESS 0020 0022 0024 8838 0024 002¢ 0025 0030 0032 0036 0038-0032 28-31 ¢ 8 9 10 an 12 13 16 17 1s 49 20 2. 22 23 24 25 27 9901 Control mrt 17 INT? 18 N73 9 INTs 8 INTS 7 mre 6 INT7 (P15) 34 INTS (P14) 33 INT9 (P13) 32 INTLO (P12) 31 mpti (p11) 30, INTI2 (P12) 29 15 INTL3-INT15 28,27 423 9901 1/0 MAPPING rt 2902 pre PO 38 PL 7 P2 26 8 8 PS 20 De 10 P7 (INTLS) 23 PB (INT14) 27 P10(INTI2) 28 P11 (INTI1) 30 P12-P15 31-34 FUNCTION Control, Bxternal video Display Processor Vertical Syne QLock Interrupt, Keyboard SENTER" line, Joystick "PIRE" Keyboard "L" stick “hect” Keyboard "P" line, Joy- stick "Right" Keghoard "0* stick "Down" Reyboard "SHIFT" line, Joystick "UP" Reyboard space line Keyboard "Q* line Keyboard "1" line Hot Usod Reserved Not Used line, goy- line, aay- rune Reserved Reserved tna (ESB) of Keyboard Befect aig of Keyboard select BIE) (usp) of Keyboard Select” i Not used Gaceotte Control 2 Cassette Control 2 Audio Gate Mag Tape Out Mag Tape Input Not used