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Cs2100 4 Logic Gates and Circuits

This document discusses logic gates and circuits. It begins by defining common logic gate symbols such as AND, OR, NOT, NAND, NOR, XOR and XNOR. It then explains how to draw and analyze basic logic circuits using these gates. The document notes that NAND and NOR gates are universal, meaning any logic function can be implemented using only those gate types. It also covers sum-of-products and product-of-sums logic minimization and shows how to implement these using NAND/NOR circuits. Finally, it briefly discusses programmable logic arrays and read-only memory.

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246 views27 pages

Cs2100 4 Logic Gates and Circuits

This document discusses logic gates and circuits. It begins by defining common logic gate symbols such as AND, OR, NOT, NAND, NOR, XOR and XNOR. It then explains how to draw and analyze basic logic circuits using these gates. The document notes that NAND and NOR gates are universal, meaning any logic function can be implemented using only those gate types. It also covers sum-of-products and product-of-sums logic minimization and shows how to implement these using NAND/NOR circuits. Finally, it briefly discusses programmable logic arrays and read-only memory.

Uploaded by

amanda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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CS2100 Computer Organisation

Logic Gates and Circuits

LOGIC GATES AND CIRCUITS

Gate Symbols
Inverter/AND/OR/NAND/NOR/XOR/XNOR
Drawing and Analysing Logic Circuits
Universal Gates
SOP and NAND Circuits
POS and NOR Circuits
Programmable Logic Array

AY11/12 Sem 1

Logic Gates and Circuits

LOGIC GATES

Gate symbols
a

AND
OR
NOT
NAND
NOR
EXCLUSIVE OR
AY11/12 Sem 1

Symbol set 2

Symbol set 1

b
a
b
a
a
b
a
b
a
b

ab

a+b

a'

(ab)'

(a+b)'

ab

Logic Gates and Circuits

(ANSI/IEEE Standard 91-1984)


a
&
ab
b
a
b
a
a
b
a
b
a
b

a+b

a'

&

(ab)'

(a+b)'

=1

ab
3

INVERTER/AND/OR GATES

Inverter (NOT gate)

A'

A'

A'

0
1

AND gate

AB

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OR gate

AB

A+B

Logic Gates and Circuits

A+B

NAND GATE

NAND gate

(A B)'

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(A B)'

(A B)'

NAND

Logic Gates and Circuits

Negative-OR

NOR GATE

NOR gate

(A + B)'

AY11/12 Sem 1

(A + B)'

(A + B)'

NOR

Logic Gates and Circuits

Negative-AND

XOR GATE

XOR gate
A
B

AY11/12 Sem 1

AB

Logic Gates and Circuits

AB

XNOR GATE

XNOR gate
A

(A B)'

B
XNOR can be represented by
(Example: A B)

AY11/12 Sem 1

Logic Gates and Circuits

(A
B)'

LOGIC CIRCUITS (1/2)


Fan-in: the number of inputs of a gate.
Gates may have fan-in more than 2.

Example: a 3-input AND gate

Given a Boolean expression, we may implement it as a logic


circuit.
Example: F1 = xyz' (note the use of a 3-input AND gate)

x
y
z
AY11/12 Sem 1

F1
z'
Logic Gates and Circuits

LOGIC CIRCUITS (2/2)

Example: F2 = x + y'z
x

F2

y'
z

x
y

y'z

If complemented literals
are available

F2
y'z
If complemented literals
are not available

Example: F3 = xy' + x'z


x
y'
x'
z

AY11/12 Sem 1

x
y

x.y'

x.y'
F3

F3
x'.z

Logic Gates and Circuits

x'.z

10

ANALYSING LOGIC CIRCUITS

Given a logic circuit, we can analyse it to obtain the logic


expression.

Example: Given the logic circuit below, what is the Boolean


expression of F4?
A
B

F4

F4 = ?

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Logic Gates and Circuits

11

QUICK REVIEW QUESTIONS (1)


DLD

page 77
Questions 4-1 to 4-4.

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Logic Gates and Circuits

12

UNIVERSAL GATES

AND/OR/NOT gates are sufficient for building any Boolean


function.

We call the set {AND, OR, NOT} a complete set of logic.

However, other gates are also used:


Usefulness (eg: XOR gate for parity bit generation)
Economical
Self-sufficient (eg: NAND/NOR gates)

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Logic Gates and Circuits

13

NAND GATE

{NAND} is a complete set of logic.

Proof: Implement NOT/AND/OR using only NAND gates.


x

x
y
x

x'

(xx)' = x' (idempotency)

(xy)'
xy
x'
x+y

y
AY11/12 Sem 1

((xy)'(xy)')' = ((xy)')' (idempotency)


= xy
(involution)

((xx)'(yy)')' = (x'y')'
(idempotency)
= (x')'+(y')' (DeMorgan)
= x+y
(involution)

y'
Logic Gates and Circuits

14

NOR GATE

{NOR} is a complete set of logic.

Proof: Implement NOT/AND/OR using only NOR gates.


x

y
x
y
AY11/12 Sem 1

x'

(x+x)' = x' (idempotency)

x'
xy

((x+x)'+(y+y)')' = (x'+y')' (idempotency)


= (x')'(y')' (DeMorgan)
= xy
(involution)

x+y

((x+y)'+(x+y)')' = ((x+y)')' (idempotency)


= x+y
(involution)

y'
(x+y)'

Logic Gates and Circuits

15

QUICK REVIEW QUESTIONS (2)


DLD

page 77
Questions 4-6 to 4-8.

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Logic Gates and Circuits

16

SOP AND NAND CIRCUITS (1/2)

An SOP expression can be easily implemented using


2-level AND-OR circuit
2-level NAND circuit

Example: F = AB + C'D + E
Using 2-level AND-OR circuit
A
B
C

D
E

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Logic Gates and Circuits

17

SOP AND NAND CIRCUITS (2/2)

Example: F = AB + C'D + E
Using 2-level NAND circuit
A
B

A
B

C
D

C
D

E
A
B
C
D

E
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Logic Gates and Circuits

18

POS AND NOR CIRCUITS (1/2)

A POS expression can be easily implemented using


2-level OR-AND circuit
2-level NOR circuit

Example: G = (A+B) (C'+D) E


Using 2-level OR-AND circuit
A
B
C
D

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Logic Gates and Circuits

19

POS AND NOR CIRCUITS (2/2)

Example: G = (A+B) (C'+D) E


Using 2-level NOR circuit
A
B

A
B

C
D

C
D

E
A
B
C
D

E
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Logic Gates and Circuits

20

READING ASSIGNMENT
Propagation

Delay

Read up DLD section 4.5, pg 69 71.


Integrated

Circuit Logic Families

Read up DLD section 4.6, pg 71 72.

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Logic Gates and Circuits

21

INTEGRATED CIRCUIT (IC) CHIP

14
13
12
11

10

Logic Gates and Circuits

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GND

Example of a 74LS00 chip:


Quad NAND gates.

Vcc = 5v

22

PROGRAMMABLE LOGIC ARRAY

A programmable integrated
circuit implements sum-ofproducts circuits (allow
multiple outputs).

2 stages
AND gates = product terms
OR gates = outputs

Connections between inputs


and the planes can be
burned.

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Logic Gates and Circuits

23

PLA EXAMPLE (1/2)

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Logic Gates and Circuits

24

PLA EXAMPLE (2/2)

Simplified representation of previous PLA.

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Logic Gates and Circuits

25

READ ONLY MEMORY (ROM)

Similar to PLA
Set of inputs (called addresses)
Set of outputs
Programmable mapping between inputs and outputs

Fully decoded: able to implement any mapping.

In contrast, PLAs may not be able to implement a


given mapping due to not having enough minterms.

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Logic Gates and Circuits

26

END

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Logic Gates and Circuits

27

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